Oscillator/Pll Clock Module - Texas Instruments C28 Series Student Manual

Oscillator/PLL Clock Module

C28x Oscillator / PLL Clock Module
C28x Oscillator / PLL Clock Module
X1 /CLKIN
X1 /CLKIN
crystal crystal
X2
X2
XF_XPLLDIS
XF_XPLLDIS
The OSC/PLL clock module provides all the necessary clocking signals for C28x devices. The
PLL has a 4-bit ratio control to select different CPU clock rates. Two modes of operation are
supported – crystal operation, and external clock source operation. Crystal operation allows the
use of an external crystal/resonator to provide the time base to the device. External clock source
operation allows the internal oscillator to be bypassed, and the device clocks are generated from
an external clock source input on the X1/CLKIN pin. The watchdog receives a clock signal from
OSCCLK. The C28x core provides a SYSCLKOUT clock signal. This signal is prescaled to
provide a clock source for the on-chip peripherals through the high-speed and low-speed
peripheral clock prescalers.
C28x - System Initialization
PLLCR @ 0x007021
PLLCR @ 0x007021
Watchdog
Watchdog
Module
Module
•
•
PLL PLL
Clock Module
Clock Module
4 4 - - bit PLL Select bit PLL Select
DIV3 DIV3 DIV2 DIV2
0 0
0 0
0 0 0 0
0 0
0 0
0 0 0 0
PLLCR PLLCR
0 0 1 1
bits 15:4 bits 15:4
0 0 1 1
reserved
reserved
0 0 1 1
0 1
0 1
1 1 0 0
1 0
1 0
1 1 0 0
(lab file: (lab file: SysCtrl SysCtrl
CLKIN
CLKIN
OSCCLK OSCCLK
1
1
PLLCLK PLLCLK
/2
/2 0
0
DIV1 DIV1 DIV0 DIV0 Clock Frequency (CLKIN) Clock Frequency (CLKIN)
0 0 OSCCLK x 1 / 2 (no PLL) *
0 0 OSCCLK x 1 / 2 (no PLL) *
0 0 1 1 OSCCLK x 1 / 2 OSCCLK x 1 / 2
1 0 OSCCLK x 2 / 2
1 0 OSCCLK x 2 / 2
1 1 1 1 OSCCLK x 3 / 2 OSCCLK x 3 / 2
0 0 0 0 OSCCLK x 4 / 2 OSCCLK x 4 / 2
0 0 1 1 OSCCLK x 5 / 2 OSCCLK x 5 / 2
1 1 0 0 OSCCLK x 6 / 2 OSCCLK x 6 / 2
1 1 OSCCLK x 7 / 2
1 1 OSCCLK x 7 / 2
0 0 0 0 OSCCLK x 8 / 2 OSCCLK x 8 / 2
0 1 OSCCLK x 9 / 2
0 1 OSCCLK x 9 / 2
1 1 0 0 OSCCLK x 10 / 2 OSCCLK x 10 / 2
Oscillator/PLL Clock Module
.c) .c)
C28x
C28x
Core Core
SYSCLKOUT SYSCLKOUT
• • • •
HISPCP HISPCP LOSPCP LOSPCP
HSPCLK LSPCLK
HSPCLK LSPCLK
* default * default
5 - 3