Sony DNW-A75 Maintenance Manual page 231

Appendix C
Circuit Description and Overall Block Diagram
The following block diagrams are explained after circuit description.
. Overall (1/3) : Signal Processing System................................................................................... C-8
. Overall (2/3) : System/Servo Control System (1/2) ................................................................... C-10
. Overall (3/3) : System/Servo Control System (2/2) and DT control System ............................. C-12
(1) Video Signal Processing System (CP-334, DEC-110, SDI-41, and VPR-47 Boards)
Recording system
The inputted analog composite video signal and the inputted analog component video signal from the
VIDEO INPUT connectors are sent from the CP-334 board to the DEC-110 board and converted from
analog to digital. After that, the analog composite video signal is converted into a digital component
signal (parallel) by the composite decode block, and the analog component video signal into a digital
component signal (serial) by the multiplexer.
Only the digital component signal selected as a video input signal is sent from the DEC-110 board to the
input TBC block on the SDI-41 board.
The inputted SDI signal from the SDI INPUT connector is inputted to the SDI-41 board and converted
from serial to parallel. After that, in an SDI Decode Process block, an SDI video signal is extracted, and
EAV, SAV, video index, etc are detected.
The SDI video signal is also sent to the input TBC block on the SDI-41 board.
The input TBC block on the SDI-41 board makes an input video signal (the SDI video signal or the
digital component signal from the DEC-110 board) synchronize with the reference internal clock of this
unit.
The input video signal output from the input TBC block is sent to the VPR-47 board through setup
remove and VITC generation blocks.
The setup remove block removes a setup level only when an input video is in the 525/60 mode.
The VITC generation block reads VITC and sets data for recording.
The input video signal sent to the VPR-47 board is sent through a frame control block to the DPR-118
board as REC data. The input video signal is also sent to the video processing block as EE data (E-E
video signal).
Playback system
A Betacam SX video PB signal is reconstructed on the DPR-118 board. After that, the signal is sent to the
video processing block through a video jog processing block.
After an analog Betacam video PB signal is reconstructed on the DM-89, TBC-24, and TBC-23A boards,
it is sent to the video processing block on the VPR-47 board.
The video jog processing block converts the signal sent intermittently in the VAR/JOG PB mode into a
continuous signal. In addition to the Betacam SX video signal or analog Betacam (Betacam/Betacam SP)
video PB signal described above, the E-E video signal is also input to the video processing block.
The SX video PB signal (signal output from the video jog processing block) or analog Betacam video PB
signal is also input to the freeze memory block. The video data memorized in the freeze memory block is
read in the freeze mode and input to the video processing block.
Each processing (gain adjustment, chroma phase adjustment, blanking addition, and line adder) is
performed in the video processing block. The obtained information is sent to an encode block as the PB
video signal (digital component video signal).
And when playing back the analog Betacam video PB only, the PB video signal input is also send to a
frame control block as the SDTI outputs (optional BKNW-118/124). On the DPR-118 board, the bit rate
of the PB video signal output from the frame control block is compressed into 1/10. After that, the
compressed signal is sent to the DPR-119 board of BKNW-118 or DPR-150 board of BKNW-124.
C-1
DNW-A75/A75P