Table of Contents
Advertisement
DPR-337F (2/16)
MST 74MHz
Pd= MAX:250mW@25 degree C
+5V-D
+3.3V_DRV
IC300
R300
NJM2878F3-33(TE2)
10
(1/10W)
(4.32V)
5
4
VIN
VOUT
R302
R301
22k
1
3
C304
C305
10
CTL
NC
47uF
1uF
(1/10W)
GND
6.3V
6.3V
3216
C300
2
10uF
2012
R312
22
GND
R310
1k
from SY FPGA
015-AB3
MST-74M-CLK
IC322
NJM2878F3-33(TE2)
5
4
VIN
VOUT
R360
C339
C340
22k
1
3
47uF
1uF
CTL
NC
6.3V
6.3V
GND
3216
MST 27MHz
2
R313
22
GND
R311
1k
GND
from SY FPGA
015-AB8
MST-27M-CLK
R358
22
C336
10pF
R359
NM
1k
GND
+3.3V
RB300
100k
IC302
TC74VHC245FT(EKJ)
RB301
R314
220
47k
WR_in
1
2
2
A1
3
RD_in
3
4
A2
4
5
6
A3
MST-RESET_in
7
8
5
A4
6
A5
7
A6
8
A7
9
A8
R315
47
19
OE
1
DIR
RESET
+3.3V
+3.3V
+3.3V
C303
0.1uF
R316
47
R309
IC321(1/4)
47k
2
TC7WH14FK
GND
R317
VDD
1
1
7
6
2
100
OUT
IC321(2/4)
4
5
TC7WH14FK
IC301
NC
CD
GND
R3112N281A-TR-FE
C310
3
C306
0.01uF
0.01uF
GND
(0.02uF-> 90mS)
GND
4.49 x C(uF)[S]
+3.3V
(N-ch_Open_Drain_Output)
IC321 (3/4)
TC7WH14FK
VCC
3
5
GND
GND
GND
HXCU-FB70
C314
GND
MST-74M
0.1uF
C318
0.1uF
FB302
TP301
4
13
R320
16
VDD1
VDD2
2
100
FBIN
1Y0
R322
22
C307
3
1Y1
74M-CLK-FPGA-SY
014-G1
10pF
1
14
NM
RB325
5
6
22
(3/4)
CLKIN
1Y2
74M-CLK-FPGA-HDMI
007-W4
15
RB325
7
8
22
(4/4)
1Y3
74M-CLK-FPGA-POST
004-H7
9
6
R325
22
S1
2Y0
74M-CLK-FPGA-DEMUX
003-O4
GND
7
R326
22
R304
2Y1
016-S5
74M-CLK-AT
22
8
10
RB325
1
2
22
(1/4)
S2
2Y2
74M-CLK-PROCYON
005-Z6
11
RB325
3
4
22
(2/4)
2Y3
74M-CLK-SDI
006-C2
R307
GND1
GND2
2.2k
C312
0.1uF
5
12
IC304
CDCVF25081PWR
GND
GND
C332
GND
0.1uF
C333
0.1uF
FB300
MST-27M
TP300
4
13
R319
100
16
VDD1
VDD2
2
FBIN
1Y0
3
RB324
C308
1Y1
10pF
22
NM
1
14
1
2
CLKIN
1Y2
27M-CLK-AT
016-S5
R303
15
3
4
100
1Y3
27M-CLK-SDI
006-C2
9
6
5
6
S1
2Y0
27M-CLK-FPGA-HDMI
007-W4
7
7
8
2Y1
27M-CLK-FPGA-POST
004-H7
8
10
S2
2Y2
27M-CLK-FPGA-SY
014-G2
11
R321
2Y3
22
C317
GND1
GND2
0.1uF
5
12
IC319
CDCVF25081PWR
GND
C313
GND
0.1uF
C334
0.1uF
FB305
4
13
16
VDD1
VDD2
2
R355
FBIN
1Y0
22
3
R357
1Y1
27M-CLK-SVIDEO
010-R5
100
1
14
1
2
27M-CLK-844
CLKIN
1Y2
009-B2
15
3
4
1Y3
27M-CLK-ENCODER
R308
10k
9
6
5
6
S1
2Y0
27M-CLK-DA-COMPOSITE
009-O3
7
7
8
2Y1
27M-CLK-PROCYON
005-Z6
8
10
RB303
S2
2Y2
GND
11
22
C335
2Y3
GND1
GND2
0.1uF
5
12
IC320
CDCVF25081PWR
GND
+3.3V
C315
0.1uF
20
RB302
GND
47
VCC
18
1
2
CPU-WR
B1
17
3
4
CPU-RD
B2
16
5
6
B3
15
7
8
B4
14
B5
13
B6
12
B7
11
B8
GND
10
GND
R332
100
RESET_SY
014-K1
RESET_DEMUX
003-K4
R333
100
R334
100
RESET_ENC_POST
R318
47k
IC312 (1/2)
TC7SZ08FU(TE85R)
R335
2
100
4
1
RESET_HDMI
007-W4
+2.5V
R329
47k
2
R331
4
100
1
PROCYON_RST
005-U5
R330
IC313
(1/2)
100
TC7SZ08FU(TE85R)
POWER_ON-RESET
+3.3V
+2.5V
VCC
C319
VCC
0.1uF
C338
C316
GND
0.1uF
0.1uF
GND
IC312 (2/2)
IC313
(2/2)
GND
IC321(4/4)
GND
TC7SZ08FU(TE85R)
TC7SZ08FU(TE85R)
TC7WH14FK
CLOCK
CPU_I/F
from/to AT Board
+3.3V
016-N5
CPU_BUS
SDA_in/out
SCL_in
FPGA(SY)
FPGA(HDMI)
FPGA(POST)
FPGA(DEMUX)
AT Board
PROCYON
GENNUM PS
CPU-CK_in
IC307 (2/2)
TC7SZ08FU(TE85R)
+3.3V
VCC
GND
AT Board
GENNUM SDI
FPGA(HDMI)
FPGA(POST)
FPGA(SY)
RB305
100k
BUS(0)_in
BUS(1)_in
BUS(2)_in
BUS(3)_in
BUS(4)_in
BUS(5)_in
ADV7320
BUS(6)_in
Flip-Flop for SD844
BUS(7)_in
009-B10,009-G1
ENCODER(CXD9184)
THS5661 D/A for COMPOSITE OUT
PROCYON
RB306
100k
ADDR(0)_in
ADDR(1)_in
ADDR(2)_in
ADDR(3)_in
ADDR(4)_in
ADDR(5)_in
ADDR(6)_in
ADDR(7)_in
FPGA SY
RB304
100k
FPGA DeMUX
ADDR(8)_in
ADDR(9)_in
ADDR(10)_in
004-H7,009-G1,010-B9,010-R5
CS-DPR_in
ENCORDER
FPGA POST
ADV7320
FPGA HDMI
003-V6,004-P5,005-U5,007-AA6,014-F5
+3.3V
R343
10k
R341
10
2
4
R342
1
+3.3V
C325
10
0.1uF
IC310 (1/2)
TC7SH08FU
8
R337
100
GND
5
VCC
3
SDA
A2
6
2
SCL
A1
ADDRESS:010
7
1
R338
100
WP
A0
IC309
VSS
CAT24C02WI-GT3
4
GND
+3.3V
CPU-CK
CL300
0.8
IC314
(1/2)
2
R340
R336
4
22
TC7SZ08FU(TE85R)
10
1
IC315
(1/2)
IC307 (1/2)
TC7SZ08FU(TE85R)
R339
TC7SZ08FU(TE85R)
2.2k
IC316
(1/2)
GND
TC7SZ08FU(TE85R)
IC314
(2/2)
IC315
(2/2)
TC7SZ08FU(TE85R)
TC7SZ08FU(TE85R)
+3.3V
+3.3V
IC317
(1/2)
TC7SZ08FU(TE85R)
C320
VCC
C326
VCC
C327
0.1uF
0.1uF
0.1uF
GND
GND
IC318
(1/2)
TC7SZ08FU(TE85R)
GND
GND
GND
+3.3V
RB323
+3.3V
100k
+3.3V
IC306
RB310
FB304
TC74VHC245FT(EKJ)
100k
C323
0.1uF
RB318
RB311
20
GND
47
220
2
VCC
18
1
2
1
2
CPU-D0
A1
B1
3
4
3
17
3
4
CPU-D1
A2
B2
4
16
5
6
5
6
CPU-D2
A3
B3
+3.3V
5
15
7
8
7
8
CPU-D3
A4
B4
C328
1
2
6
14
1
2
CPU-D4
0.1uF 16V
A5
B5
7
13
3
4
3
4
CPU-D5
A6
B6
8
12
5
6
5
6
CPU-D6
A7
B7
16
GND
7
8
9
11
7
8
CPU-D7
A8
B8
1
VCC
15
CPU-A8
A
Y0
RB312
RB319
CPU-A9
2
14
220
19
B
Y1
47
OE
3
13
CPU-A10
1
C
Y2
DIR
12
GND
Y3
6
11
10
G1
Y4
4
10
CS-DPR
G2A
Y5
5
9
GND
G2B
Y6
7
+3.3V
CPU-RD
Y7
GND
8
IC311
IC308
+3.3V
TC74VHC245FT(EKJ)
TC74LCX138FT(EKJ)
RB313
C324
100k
0.1uF
GND
RB314
20
RB320
220
GND
47
1
2
2
VCC
18
1
2
CPU-A0
A1
B1
3
17
3
4
3
4
CPU-A1
A2
B2
4
16
5
6
5
6
CPU-A2
A3
B3
7
8
5
15
7
8
CPU-A3
A4
B4
6
14
1
2
1
2
CPU-A4
A5
B5
7
13
3
4
3
4
CPU-A5
A6
B6
5
6
8
12
5
6
CPU-A6
A7
B7
9
11
7
8
7
8
CPU-A7
A8
B8
RB321
RB315
220
19
47
OE
1
DIR
GND
10
GND
+3.3V
IC305
+3.3V
TC74VHC245FT(EKJ)
RB307
C322
0.1uF
100k
RB308
20
RB316
GND
220
47
2
VCC
18
1
2
1
2
CPU-A8
A1
B1
3
17
3
4
3
4
CPU-A9
A2
B2
5
6
4
16
5
6
CPU-A10
A3
B3
5
15
7
8
7
8
CS-DPR
A4
B4
6
14
1
2
1
2
A5
B5
3
4
7
13
3
4
A6
B6
8
12
5
6
5
6
A7
B7
7
8
9
11
7
8
A8
B8
RB309
RB317
47
220
19
OE
1
DIR
GND
10
GND
+3.3V
C329
0.1uF
GND
VCC
GND
IC310 (2/2)
SDA
TC7SH08FU
SCL
GND
from/to ENCODER
IIC2-BUS
009-G4
IC316
(2/2)
IC317
(2/2)
TC7SZ08FU(TE85R)
TC7SZ08FU(TE85R)
+3.3V
+3.3V
VCC
C330
VCC
C331
0.1uF
0.1uF
GND
GND
+3.3V
GND
GND
R344
10k
2
R346
to SY FPGA
4
10
1
CP-CLK_SY
014-G2
2
R347
to DEMUX FPGA
4
10
1
CP-CLK_DEMUX
003-L4
2
R348
to POST FPGA
10
4
1
CP-CLK_POST
004-H7
R349
2
to HDMI FPGA
10
4
1
CP-CLK_HDMI
007-W4
+2.5V
R345
10k
R350
2
to Procyon
10
4
005-U3
1
CP-CLK_ZXCV
+2.5V
IC318
(2/2)
TC7SZ08FU(TE85R)
VCC
C321
RB322
0.1uF
GND
100k
GND
+3.2V
CPU_I/F
003-L4,004-T10,005-U1,007-G1,014-K1
CS_ZXCV
CS_DEMUX
CS_POST
CS_SY
CS_HDMI-PLD
CS_HDMI-HIDE
CS_HIDEO-PGM
CLK Driver
CPU_I/F ,RESET
DPR-337F (2/16)
BOARD NO. 1-885-532-21
DPR-337_2
9-17
Advertisement
Table of Contents
