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The INTR SER V (Interrupt Service) Indicator
turns on
when a hardware forced branch instruction
IS
being executed
to enable service of the highest priority interrupt level that
is on.
The
CS
SER V (Cycle Steal Service) Indicator
is on during
cycle steal operations of a data channel.
The
AUX STOR (CE Storage) Indicator
is on when CE
storage is being used. CE storage is provided for Customer
Engineering use.
The
OP (Operation) Code Check Indicator
turns on when
an invalid operation code is detected in the OP reEister. This
indicator is turned off and the check indicator is turned on
when the next main storage cycle is initiated. This allows
the OP code check indicator to indicate any subsequent
error.
The STOR PROT (Storage Protect) Check Indicator
is
turned on when an attempt is made to write into a read-
only location of main storage. This indicator is turned off
and the check indicator is turned on when the next main
storage cycle is initiated. This allows the STOR PROT check
indicator to indicate any subsequent error.
The
PTY (Parity) Check Indicator
is turned on when a
parity check (even number of bits on) is detected in the
18-bit word transfer between the B-register and main
storage. This indicator is turned off and the check indicator
is turned on when the next main storage cycle is initiated.
This allows the PTY check indicator to indicate any
subsequent error.
The
Clock Indicators
(0 through 7) show the advance of the
basic processor-controller clock during single step opera-
tions.
The Cycle Indicators
(I I . 12, E, and E I ) show the progress
of an instruction during single step or single cycle operations.
The
Timers Indicators
(A, B, and C) show the status of
their respective interval timers. An on condition indicates
that the timer is in operation.
The Internlpt Levels Indicators (0
through
23,
check,
trace, and CE) show the status of their respective interrupt
levels. The indicator being on indicates that the level is
requesting service.
The
OP (Operation) Code Indicators (0
through
4)
display
the operation code of each instruction.
The F (Format) Indicator
is on when a two-word instruction
is being executed.
The
Tag Indicators
reflect the index registers used in modi-
fication of the address portion of an instruction.
The
IA (Indirect Addressing) Indicator
(bit 8) is on when
bit 8 of the instruction is also on. This bit only indicates
indirect addressing if the F-bit is on.
The
BO (Branch Out) Indicator
is on when there is a bit
in position 9 of an instruction.
The Carry and Overflow Indicators
are turned on individ-
ually when their respective conditions occur in the
A-register.
DATA FLOW INDICATORS (Figure 7)
The
Address Register Indicators
display the data in the
register selected by the display address register switch. The
selected register is displayed each time the processor-
controller comes to a stop or wait condition.
The
I (Instruction) Register Indicators
display the contents
-
-
-
-
-
0
I
2
3
4
5
6
7
8
9
10
II
12
13
14
15
I
REGISTE,~
~~~~ ~~~~ ~~~~ ~~~
~
0
I
2
3
4
5
6
7
8
9
10
II
12
13
14
15
B REGISTER
~~~~ ~~~~ ~~~~ ~~~~
(\
1
?
1
.4
C;
f,
7
8
9
10
II
12
13
14
15
D REGISTER
~~~~I~~~~
~~~~ ~~~~
0
I
2
3
4
5
6
7
8
9
10
II
12
13
14
15
A REGISTER
~~~~ ~~~~ ~~~~ ~~~~
I
I
DATA REGISTER
o
I
2
3
I
4
5
6
7
I
8
9
10
II
I
12
"i3
14
i5
I
~
@
~ ~I~ ~ ~ ~I~
@)
~ ~I~ ~ ~ ~l
Figure 7. Data Flow Indicators
12
IBM 1800 Operating Procedures
of the I-register. The I-register holds the address of the
next sequential instruction and is automatically incremented
for sequential instruction operation.
The B (Storage Buffer) Register Indicators
display the
contents of the B-register. The B-register is used to buffer
all word transfers with main storage.
The
D (Arithmetic Factor) Register Indicators
display the
contents of the D-register. The D-register is used to hold
one operand of any arithmetic or logical operation. The
A-regIster provides the other operand.
The
A (Accumulator) Register Indicators
display the
contents of the A-register. The A-register contains the
results of any arithmetic and logical operation. It can be
loaded from or stored into main storage,.shifted right or
left, and otherwise manipulated by specific arithmetic and
logical instructions.
TIle
Data Register Indicators
display the contents of the
register selected by the display data register switch. The
selected register is displayed each time the processor-
controller comes to a stop or wait condition.
I
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