Table of Contents
Advertisement
TOGGLE SWITCHES (Figure 5)
The Sense and Program Switches
are normally used for
communication with the program. The contents of these
eight switches may be stored in bit positions 0 through 7
of the A-register or a main storage location as directed
by the stored program.
The Operations Monitor Switch,
when on, enables the
operations monitor. The off position disables the opera-
tions monitor.
The Disable Interrupt Switch
is used to mask or disable
all interrupt levels. It is used to choose the time at which
the program may be interrupted during program analysis.
SENSE
PROGRAM
OPERATIONS
DISABLE
CHECK
WRITE STOR
MONITOR
INTERRUPT
STOP
PROT BITS
0
ON
ON
ON
YES
~ ~ ~ ~
~ ~
; ;
~
;
~ ~
OFF
Off
OFF
NO
DATA ENTRY SWITCHES
3
5
6
7
8
10
II
12
13
14
15
;
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
Figure 5. Console Toggle Switches
The highest priority level on and unmasked (not disabled)
is serviced when the switch is turned off.
The Check Stop Switch
is used to stop processor-controller
operation when one of the following conditions occurs:
operation code check, storage protect check, or parity
check. The stop occurs at the end of the main-storage cycle
in which the check is detected. The appropriate error light
will be on. START must be pressed to restart the system.
The preceding check conditions initiate an internal
(check) interrupt if the check stop switch is off.
A clear storage function is stopped when the check stop
switch is on and a parity check is detected.
The Write STaR PROT (Storage Protect) Bits Switch
enables the writing or clearing of storage protect bits when
the switch is on. A parity error may occur if the position of
this switch is changed while the processor-controller is
running.
The Data Entry Switches
provide a means of entering data
under either manual or program control. Under program
control, the contents of the switches can be stored in main
storage or the A-register. Under manual control, the contents
of the switches can be stored at the address specified by the
I-register by pressing START, or loaded into the I-register by
pressing LOAD I provided the mode switch is on LOAD.
STATUS INDICATORS (Figure 6)
ARITH
SHIFT
ADD
ARITH
ZERO
BRANCH
STOR PROT
PTY BIT
ClL
ClL
SIGN
REM
BIT
~
~
~
~
~
~
~
~
INTR
CS
AUX
OP CODE
STOR PROT PTY CHECK
SERV
SERV
STOR
CHECK
CHECK
~
~
~
~
~
~
~
~
CLOCK
CYCLE
TIMERS
0
I
2
3
4
5
6
7
II
12
IA
E
EI
A
B
C
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
INTERRUPT
LEVELS
0
I
2
3
4
5
6
7
8
9
10
II
12
13
14
15
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
16
17
18
19
20
21
22
23
CHECK
TRACE
CE
~
~
~
~
~
~
~
~
~
~
~
~
OP CODE
F
TAG
IA
80
CAR
OHO
0
I
2
~I~
5
6
7
8
9
10
II
12
13
14
15
~
~
~
~
~
~
~
~
~
~I~
~
~
~
Figure 6. Status Indicators
The ARITH CTL (Arithmetic Control) Indicator
turns on
during arithmetic operations.
The Shift CTL (Control) Indicator
turns on during shift
operations.
The Add Indicator
is on during add operations.
The ARITH SIGN (Arithmetic Sign) Indicator
turns on when
bit position 0 in the A-register does not initially equal bit
position 0 in the B-register.
The Zero REM (Remainder) Indicator
is on when the
A-register contains a 0 balance during a divide instruction.
The Branch Indicator
is on during branch instructions.
The STaR PROT (Storage Protect) Bit Indicator
is on when
a storage protect bit is transferred with the 16 data bits
between the B-register and main storage.
The PTY (Parity) Bit Indicator
turns on when a parity bit
is transferred with the 16 data bits between the B-register
and main storage.
IBM 1801/1802 Processor-Controller
11
Advertisement
Table of Contents
