Table of Contents
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Chapter 3
Signal Connections
V
IH
CLK
V
IL
V
IH
GATE
V
IL
V
OH
OUT
V
OL
NI PCI-1200 User Manual
•
82C53 digital output specifications (referenced to DGND):
–
V
output logic high voltage
oh
–
V
output logic low voltage
ol
–
I
output source current, at V
oh
–
I
output sink current, at V
ol
Figure 3-16 shows the timing requirements for the GATE and CLK input
signals and the timing specifications for the 82C53 OUT output signals.
t
sc
t
gsu
t
gwh
t
outg
t
clock period
sc
t
clock high level
pwh
t
clock low level
pwl
t
gate setup time
gsu
t
gate hold time
gh
t
gate high level
gwh
t
gate low level
gwl
t
output delay from clock
outc
t
output delay from gate
outg
Figure 3-16. General Purpose Timing Signals
The GATE and OUT signals in Figure 3-16 are referenced to the rising edge
of the CLK signal.
3.7 V min
oh
ol
t
pwh
t
gh
380 ns minimum
230 ns minimum
150 ns minimum
100 ns minimum
50 ns minimum
150 ns minimum
100 ns minimum
300 ns maximum
400 ns maximum
3-26
—
0.45 V max
—
—
–0.92 mA max
—
2.1 mA max
t
pwl
t
gwl
t
outc
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