Memory Access; On-Chip L3 Cache Innovation And Intelligent Cache - IBM Power Systems S822LC Technical Overview And Introduction

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The architecture of the POWER8 processor, with its larger caches, larger cache bandwidth,
and faster memory, allows threads to have faster access to memory resources, which
translates into a more efficient usage of threads. Therefore, POWER8 allows more threads
per core to run concurrently, increasing the total throughput of the processor and of the
system.

1.7.4 Memory access

On the Power S822LC server, each POWER8 module has two memory controllers, each
connected to two memory channels. Each memory channel operates at 1600 MHz and
connects to a memory riser card. Each memory riser card has a memory buffer that is
responsible for many functions that were previously on the memory controller, such as
scheduling logic and energy management. The memory buffer also has 16 MB of L4 cache.
Also, the memory riser card houses four industry-standard RDIMMs.
Each memory channel can address up to 64 GB. Therefore, the Power S822LC server can
address up to 1 TB (1024 GB) of total memory.
Figure 1-8 shows a POWER8 processor that is connected to four memory riser cards and its
components.
Memory
Riser Card
Figure 1-8 Logical diagram of the POWER8 processor connected to four memory riser cards

1.7.5 On-chip L3 cache innovation and Intelligent Cache

The POWER8 processor uses a breakthrough in material engineering and microprocessor
fabrication to implement the L3 cache in eDRAM and place it on the processor die. L3 cache
is critical to a balanced design, as is the ability to provide good signaling between the L3
cache and other elements of the hierarchy, such as the L2 cache or SMP interconnect.
SMT8
16 MB
L4
4 x RDIMMs
Cache
Buffer
Chip
160
28.8 GBps
Buffer
Chip
Memory
Controller
POWER8
SCM
Memory
Controller
Buffer
Chip
Chapter 1. Architecture and technical description
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