Memory Access; On-Chip L3 Cache Innovation And Intelligent Cache - IBM Power 720 Overview

2.1.4 Memory access

Each POWER7+ processor chips has one memory controller which uses four memory
channels. Each memory channel operates at 1066 MHz connects to four DIMMs.
In the Power 720 server, each channel can address up to 128 GB. Thus the Power 720 is
capable of addressing up to 512 GB of total memory.
In the Power 740 server, each channel can address up to 128 GB. Thus the Power 740 is
capable of addressing up to 1024 GB of total memory.
Figure 2-5 is a simple overview of the POWER7+ processor memory access structure in the
Power 720 and Power 740.
POWER7+
Figure 2-5 Overview of POWER7+ memory access structure

2.1.5 On-chip L3 cache innovation and Intelligent Cache

A breakthrough in material engineering and microprocessor fabrication enabled IBM to
implement the L3 cache in eDRAM and place it on the POWER7+ processor die. L3 cache is
critical to a balanced design, as is the ability to provide good signaling between the L3 cache
and other elements of the hierarchy, such as the L2 cache or SMP interconnect.
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IBM Power 720 and 740 Technical Overview and Introduction
Memory
Channel D
Memory
Channel C
SCM
Memory
Channel B
Memory
Channel A
DDR3 RDIMM Slot 7
DDR3 RDIMM Slot 8
Port A
Buffer
Port B DDR3 RDIMM Slot 1
DDR3 RDIMM Slot 2
DDR3 RDIMM Slot 5
DDR3 RDIMM Slot 6
Port A
Buffer
DDR3 RDIMM Slot 3
Port B
DDR3 RDIMM Slot 4
DDR3 RDIMM Slot 7
DDR3 RDIMM Slot 8
Port A
Buffer
Port B DDR3 RDIMM Slot 1
DDR3 RDIMM Slot 2
DDR3 RDIMM Slot 5
DDR3 RDIMM Slot 6
Port A
Buffer
Port B DDR3 RDIMM Slot 3
DDR3 RDIMM Slot 4
P3-Cn-C7
P3-Cn-C8
P3-Cn-C1
P3-Cn-C2
P3-Cn-C5
P3-Cn-C6
P3-Cn-C3
P3-Cn-C4
P3-Cn-C7
P3-Cn-C8
P3-Cn-C1
P3-Cn-C2
P3-Cn-C5
P3-Cn-C6
P3-Cn-C3
P3-Cn-C4