Digital I/O Circuitry; Timing I/O Circuitry; Figure 2-18. Daq-Stc Counter Diagram - National Instruments PCI E Series Programmer's Manual

Chapter 2 Theory of Operation

Digital I/O Circuitry

Timing I/O Circuitry

PCI E Series RLPM
to retransmit the same FIFO data to the DACs over and over. When the
FIFO is empty, the retransmit signal is asserted, which restores that FIFO
data to its original state.
When both DACs are used in waveform generation, the data in the FIFO is
interleaved; in other words, every alternate sample belongs to one DAC.
The PCI E Series boards have eight digital I/O lines. Each of the eight
digital lines can be individually programmed to be input or output, if used
in parallel. For serial data transfer, DIO4 is used as the serial data in pin,
and DIO0 is used as the serial data out pin.
You can use handshaking with the EXTSTROBE* pin to do either parallel
or serial data transfer. Refer to the DAQ-STC Technical Reference Manual
for more details on the DIO features.
The external strobe signal EXTSTROBE* is a general-purpose strobe
signal. Software can set the output of the EXTSTROBE* pin to either a
high or low state. EXTSTROBE* is not necessarily part of the digital I/O
circuitry, but is included here because you can use it to latch digital output
from the PCI E Series into an external device.
The DAQ-STC has two 24-bit general purpose counter/timers. The
counters are numbered 0 and 1 and are diagrammed as shown in
Figure 2-18.

Figure 2-18. DAQ-STC Counter Diagram

SOURCE
Counter
OUT
GATE
UPDOWN
2-24 © National Instruments Corporation