National Instruments PCI E Series Programmer's Manual page 7

Contents
Figures
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 2-9.
Figure 2-10.
Figure 2-11.
Figure 2-12.
Figure 2-13.
Figure 2-14.
Figure 2-15.
Figure 2-16.
Figure 2-17.
Figure 2-18.
Figure 2-19.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 5-1.
Figure 5-2.
Tables
Table 2-1.
Table 2-2.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
PCI E Series RLPM
PCI-MIO-16E-1, PCI-MIO-16E-4, and PCI-6071E Block Diagram ..... 2-1
PCI-MIO-16XE-10, PCI-6052E, and PCI-6031E Block Diagram ......... 2-2
PCI-6023E, PCI-6024E, and PCI-6025E Block Diagram ...................... 2-3
PCI-6032E and PCI-6033E Block Diagram ........................................... 2-4
PCI-MIO-16XE-50 Block Diagram........................................................ 2-5
PCI Bus Interface Circuitry Block Diagram ........................................... 2-7
Analog Input and Data Acquisition Circuitry Block Diagram ............... 2-8
ADC Timing ........................................................................................... 2-12
Timing of Scan in Example 1 ................................................................. 2-14
Multirate Scanning of Two Channels ..................................................... 2-15
Multirate Scanning of Two Channels with 1:x Sampling Rate............... 2-15
Multirate Scanning of Two Channels with 3:1:1 Sampling Rate ........... 2-16
Multirate Scanning of Three Channels with 4:2:1 Sampling Rate ......... 2-16
Multirate Scanning without Ghost .......................................................... 2-17
Occurrences of Conversion on Channel 1 in Example 3 ........................ 2-17
Successive Scans Using Ghost................................................................ 2-17
Analog Output Circuitry Block Diagram................................................ 2-20
DAQ-STC Counter Diagram .................................................................. 2-24
RTSI Bus Interface Circuitry Block Diagram ........................................ 2-26
Analog Trigger Structure ........................................................................ 4-54
DMA Structure........................................................................................ 4-57
DMA Link Chaining Mode Structure ..................................................... 4-59
EEPROM Read Timing .......................................................................... 5-2
Calibration AC Write Timing ................................................................. 5-16
PGIA Gain Set Verses Board ............................................................... 2-9
Analog Input Configuration Memory .................................................. 2-18
PCI E Series Register Map .................................................................. 3-2
PCI E Series Windowed Register Map ................................................. 3-3
PGIA Gain Selection............................................................................. 3-10
Calibration Channel Assignments......................................................... 3-12
Differential Channel Assignments ........................................................ 3-13
Nonreferenced Single-Ended Channel Assignments ........................... 3-13
Referenced Single-Ended Channel Assignments.................................. 3-14
Auxiliary Channel Assignments ........................................................... 3-15
Channel Assignments............................................................................ 3-15
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