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•
Port 0 configuration:
– Memory size is 2048KB
– Starting address is 0080 0000h
– 2-cycle latency
– 4 × 128-bit bank configuration
•
Port 1 configuration:
– Memory size is 32K bytes (this corresponds to the internal ROM)
– Starting address is 0010 0000h
– 1-cycle latency
– 1 × 256-bit bank configuration
L2 memory can be configured as all SRAM or as part 4-way set-associative cache. The amount of L2
memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration
Register (L2CFG) of the C64x+ Megamodule.
for L2. By default, L2 is configured as all SRAM after device reset.
000
All
SRAM
For more information on the operation L1 and L2 caches, see the TMS320C64x+ DSP Cache User's
Guide (literature number SPRU862).
All memory on the C6455 device has a unique location in the memory map (see
When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.
Therefore, when using a software boot mode, care must be taken such that the CPU frequency does not
exceed 750 MHz at any point during the boot sequence. After the boot sequence has completed, the CPU
frequency can be programmed to the frequency required by the application. For more detailed information
ont he boot modes, see
5.2
Memory Protection
Memory protection allows an operating system to define who or what is authorized to access L1D, L1P,
and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16
pages of L1P (2KB each), 16 pages of L1D (2KB each), and 32 pages of L2 (64KB each). The L1D, L1P,
and L2 memory controllers in the C64x+ Megamodule are equipped with a set of registers that specify the
permissions for each memory page.
Copyright © 2005–2012, Texas Instruments Incorporated
L2 mode bits
001
010
011
15/16
SRAM
31/32
63/64
SRAM
SRAM
4-way
cache
4-way
cache
4-way
Figure 5-4. TMS320C6455 L2 Memory Configurations
Section
2.4, Boot Sequence.
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SPRS276M – MAY 2005 – REVISED MARCH 2012
Figure 5-4
shows the available SRAM/cache configurations
111
L2 memory
7/8
1792K bytes
SRAM
128K bytes
4-way
cache
64K bytes
32K bytes
32K bytes
TMS320C6455
TMS320C6455
Block base
address
0080 0000h
009C 0000h
009E 0000h
009F 0000h
009F 8000h
00A0 0000h
Table
2-2).
C64x+ Megamodule
85
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