System Management Bus (Smbus* 2.0); Intel Virtualization Technology For Direct I/O (Intel Vt-D); Integrated Baseboard Management Controller (Bmc) Overview - Intel S1200SPL Technical Spesification

S1200sp family
Table of Contents

Advertisement

Intel® Server Board S1200SP Family Technical Product Specification
3.4.10

System Management Bus (SMBus* 2.0)

The Intel
C230 series chipset contains a SMBus* Host interface that allows the processor to communicate with
®
SMBus* slaves. This interface is compatible with most I
The Intel
®
C230 series chipset's SMBus* host controller provides a mechanism for the processor to initiate
communications with SMBus* peripherals (slaves). Also, the Intel
functionality, including the Host Notify protocol. Hence, the host controller supports eight command protocols
of the SMBus* interface (see System Management Bus (SMBus*) Specification, Version 2.0): Quick Command,
Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.
The Intel
C230 series chipset's SMBus* also implements hardware-based Packet Error Checking for data
®
robustness and the Address Resolution Protocol (ARP) to dynamically provide address to all SMBus* devices.
®
3.4.11
Intel
The Intel
®
C230 series chipset provides hardware support for implementation of Intel
Technology with Directed I/O (Intel
support the virtualization of platforms based on Intel
multiple operating systems and applications to run in independent partitions. A partition behaves like a Virtual
Machine (VM) and provides isolation and protection across partitions. Each partition is allocated its own subset
of host physical memory.
3.5 Integrated
Overview
The Integrated BMC is provided by an embedded ARM9* controller and associated peripheral functionality
that is required for IPMI-based server management. Firmware usage of these hardware features is platform
dependent.
The following is a summary of the Integrated BMC management hardware features that comprise the BMC:
IPMI 2.0 Compliant
400MHz 32-bit ARM9* processor with memory management unit (MMU)
Two independent 10/100/1000 Mb/s Ethernet Controllers with RMII/RGMII support
DDR2/3 16-bit interface with up to 800 MHz operation
Sixteen 10-bit ADCs
Sixteen fan tachometers
Eight Pulse Width Modulators (PWM)
Chassis intrusion logic
JTAG Master
Eight I
2
C interfaces with master-slave and SMBus* timeout support. All interfaces are SMBus* 2.0
compliant.
Parallel general-purpose I/O Ports (16 direct, 32 shared)
Serial general-purpose I/O Ports (80 in and 80 out)
Three UARTs
Platform Environmental Control Interface (PECI)
Six general-purpose timers
Interrupt controller
Multiple Serial Peripheral Interface (SPI) flash interfaces
Virtualization Technology for Direct I/O (Intel
®
VT-d). Intel
Baseboard
2
C devices. Special I
®
®
VT-d Technology consists of technology components that
®
Architecture Processors. Intel
Management
2
C commands are implemented.
C230 series chipset supports slave
®
VT-d)
®
VT-d Technology enables
Controller
®
Virtualization
(BMC)
29

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

S1200spoS1200sps

Table of Contents