Integra DTR-5.9 Service Manual page 74

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-37
Q8401 : SiI9134CTU (HDMI Deep Color Transmitter)-3/4
TERMINAL DESCRIPTION
Video and Audio Input pins
Pin Name Pin #
D0 - D11 98 - 84
D12 - D23 83 - 71
D24 - D35 70 - 56
Video and Audio Input pins
Pin Name Pin #
IDCK 88
DE 1
HSYNC 2
VSYNC 3
SCK 11
WS 10
SD0 9
SD1 8
SD2 7
SD3 6
DL0 17
DR0 16
DL1 19
DR1 18
DL2 21
DR2 20
DL3 23
DR3 22
DCLK 15
MCLK 5
SPDIF 4
Configuration / Programming Pins
Pin Name Pin #
HPD 51
RSVDL 52
INT 24
Control Pins
Pin Name Pin #
CI2CA 50
RESET# 25
CSCL 48
CSDA 49
DSCL 46
DSDA 47
Dir Description
Input These are the lower 12 bits of the 36-bit pixel bus.
These pins are highly configurable, and support multiple RGB and YCbCr formats.
Input These are the middle 12 bits of the 36-bit pixel bus.
Input These are the upper 12 bits of the 36-bit pixel bus.
Dir Description
Input Input Data clock
Input Data enable
Input Horizontal Sync input control signal
Input Vertical Sync input control signal
2
Input I S Serial Clock
2
Input I S Word Select
2
Input I S Serial data
2
Input I S Serial data
2
Input I S Serial data
2
Input I S Serial data
Input One-bit Audio data Left 0
Input One-bit Audio data Right 0
Input One-bit Audio data Left 1
Input One-bit Audio data Right 1
Input One-bit Audio data Left 2
Input One-bit Audio data Right 2
Input One-bit Audio data Left 3
Input One-bit Audio data Right 3
Input One-bit Audio Clock Input
Input Audio Input Master Clock
Input S/PDIF Audio Input.
Dir Description
Input Hot Plug Detect Input.
Input Reserved for use by Silicon Image and must be tied LOW.
Output Interrupt Output.
Dir Description
2
Input I C device address select
Input Reset Pin (Active LOW) 5V Tolerant
2
Input I C Clock
2
Bi-Di I C Data (Open Drain Output)
Bi-Di DDC Clock (Open Drain Output)
Bi-Di DDC Data (Open Drain Output)
DTR-5.9