Integra DTR-5.9 Service Manual page 65

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-28
Q8001 : FLI30502 (LCD TV Controller with Worldwide Standard Sound Processor
and HDMI Receiver)-10/12
TERMINAL DESCRIPTION
Parallel / Serial ROM interface
Pin Name
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ROM_OEN
ROM_SDI/
ROM_WEN
ROM_SCSN/
ROM_CSN
Pin # I/O Description
107
108
112
113
114 256K x 8 PROM / SRAM Address. Some of these pins also have boot strap functionality.
115 O For serial SPI ROM interface :
116 - ROM_ADDR17 is Serial Clock (ROM_SCLK)
117 - ROM_ADDR16 is Serial Data Output (ROM_SDO)
118
119
120
121
122
123
124
125
126
56
140
139
138
IO
137 External PROM / SRAM data input.
136
133
130
127
55 O External PROM / SRAM Data Output Enable.
109 O External PROM / SRAM Data Write Enable (for In-System Programming of Flash) or
Serial Data Input (SDI) for SPI ROM interface.
O
106 External PROM / SRAM Data Chip Select or Serial PROM Chip Select (ROM_SCSN) for
for SPI ROM interface.
DTR-5.9