ECS P6SEP-Me User Manual page 33

DRAM Controller 1 T WR
DRAM Controller 1 T RD
Concurrent function(MEM)
These three items define the properties and the operation of the system memory
controller. We recommend that you leave these items at the default value.
CPU Pipeline Control
Pipelining allows the system controller to signal the CPU for new memory addresses
even before all data transfers for the current cycle are complete, resulting in increased
throughput.
PCI Peer Concurrency
This item defines the operation of devices on the PCI bus. Leave this item at the
default value Enabled.
PCI Delay Transaction
If the chipset has an embedded 32-bit write buffer to support delay transaction cycles,
you can enable this item to provide compliance with PCI Ver. 2.1 specifications. We
recommend that you leave this item at the default value Enabled.
Auto Detect DIMM/PCI Clk
When this item is enabled, BIOS will disabled the clock signal of free DIMM and PCI
slots.
Spread Spectrum
When this item is enabled, it can significantly reduce the EMI (electromagnetic
interference) that your system generates by modulating the extreme values of the clock
generator pulses. Enabling this item might cause problems with timing-critical devices
such as SCSI adapters. We recommend that you leave this item at the default value
Disabled.
Default: Disabled
Default: Disabled
Default: Disabled
Default: Enabled
Default: Enabled
Default: Enabled
Default:Disabled
Default: Disabled
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