Low Power Mode; Sleep Mode - Emerson FloBoss 103 Instruction Manual

FloBoss 103/104 Instruction Manual
1.4.9
1-20
The FB100 operates with its internal batteries down to 5.4 volts dc. The
LCD becomes active when you apply input power with the proper
polarity and startup voltage (typically set greater than 8.0 volts) to the
CHG+ / CHG- connector (provided the power input fusing/protection is
operational). The battery and logical voltage tests ensure that the FB100
operates in the optimum mode.
The CPU controls the software watchdog circuit. The software arms the
watchdog timer every second. If the watchdog timer is not armed for a
period of 9 seconds, then the watchdog timer forces the FB100 to reset.
If necessary, the software automatically resets. The CPU also controls
the hardware watchdog circuit and monitors the power to the hardware.
If the battery voltage drops below 5.4 volts, the FB100 automatically
shuts down.
The FloBoss 103 monitors its orifice-metering Dual-Variable Sensor for
accurate and continuous operation. The FloBoss 104 monitors its Pulse
Interface Module.

Low Power Mode

Sleep mode places the CPU in a low power mode. Low voltage
detection circuitry (preset at a low voltage limit of 5.4 V) monitors the
battery voltage. During Sleep mode, sub-modules power down. The
FB100 enters sleep mode after one minute of inactivity on the
communication ports. Optionally, you can turn off sleep mode, which
enables your FB100 to stay active all the time.
Wake-up from sleep mode occurs when the FB100 receives either a
timed interrupt from the real-time clock or a signal from one of the
communication ports.
General Information Revised August-2017