Oscillator; Table A-15 Oscillator Characteristics; A.5.2 Oscillator - Motorola MC9S12DT256 User Manual

MC9S12DT256 Device User Guide — V03.07
A.5.1.5 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After t
fetching the interrupt vector.

A.5.2 Oscillator

The device features an internal Colpitts and Pierce oscillator. The selection of Colpitts oscillator or Pierce
oscillator/external clock depends on the XCLKS signal which is sampled during reset.By asserting the
XCLKS input during reset this oscillator can be bypassed allowing the input of a square wave. Before
asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start
from either power-on, STOP or oscillator fail. t
internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also
determines the minimum oscillator start-up time t
Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert
Frequency f
CMFA.
Conditions are shown in Table A-4 unless otherwise noted
Num C
1a C Crystal oscillator range (Colpitts)
1b C Crystal oscillator range (Pierce)
2 P Startup Current
3 C Oscillator start-up time (Colpitts)
4 D Clock Quality check time-out
5 P Clock Monitor Failure Assert Frequency
6 P External square wave input frequency
7 D External square wave pulse width low
8 D External square wave pulse width high
9 D External square wave rise time
10 D External square wave fall time
11 D Input Capacitance (EXTAL, XTAL pins)
DC Operating Bias in Colpitts Configuration on
12 C
EXTAL Pin
NOTES:
1. Depending on the crystal a damping series resistor might be necessary
2. f = 4MHz, C = 22pF.
osc
3. Maximum value is for extreme cases using high Q, low frequency crystals
4. XCLKS =0 during reset
112
CQOUT

Table A-15 Oscillator Characteristics

Rating
1(4)
4
specifies the maximum time before switching to the
. The device also features a clock monitor. A
UPOSC
Symbol Min
f
0.5
OSC
f
0.5
OSC
i
100
OSC
t
UPOSC
t
0.45
CQOUT
f
50
CMFA
f
0.5
EXT
t
9.5
EXTL
t
9.5
EXTH
t
EXTR
t
EXTF
C
IN
V
DCBIAS
the CPU starts
wrs
Typ Max Unit
16 MHz
40 MHz
µA
2 3
ms
8 100
2.5
100 200 KHz
50 MHz
ns
ns
1 ns
1 ns
7 pF
1.1
s
V