Reset, Oscillator And Pll; Startup; Table A-14 Startup Characteristics - Motorola MC9S12DT256 User Manual

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A.5 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-14 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block Guide.
Conditions are shown in Table A-4 unless otherwise noted
Num C
1
T POR release level
2
T POR assert level
3
D Reset input pulse width, minimum input time
4
D Startup from Reset
5
D Interrupt pulse width, IRQ edge-sensitive mode
6
D Wait recovery startup time
A.5.1.1 POR
The release level V
PORR
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t
clock. The fastest startup time possible is given by n
A.5.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.5.1.3 External Reset
When external reset is asserted for a time greater than PW
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.5.1.4 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.

Table A-14 Startup Characteristics

Rating
and the assert level V
PORA
no valid oscillation is detected, the MCU will start using the internal self
CQOUT
MC9S12DT256 Device User Guide — V03.07
Symbol
Min
V
PORR
V
0.97
PORA
PW
2
RSTL
n
192
RST
PW
20
IRQ
t
WRS
are derived from the V
.
uposc
the CRG module generates an internal
RSTL
Typ
Max
2.07
196
14
Supply. They are also valid
DD
Unit
V
V
t
osc
n
osc
ns
t
cyc
111

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