Q170Mcpu System Internal Configuration - Mitsubishi Q170MCPU User Manual

2 SYSTEM CONFIGURATION

2.1.2 Q170MCPU System internal configuration

PLC CPU area (CPU No.1 fixed)
PLC control
processor
PLC I/O module
24VDC
Personal computer
GX Developer
MT Developer2
(1) What is Multiple CPU system for Q170MCPU ?
A Multiple CPU system for Q170MCPU is a system in which between the PLC
CPU area and Motion CPU area are connected with the Multiple CPU high speed
bus in order to control the I/O modules and intelligent function modules.
PLC CPU area is fixed as CPU No.1, and Motion CPU area is fixed as CPU
No.2.
And, the Motion CPU area controls the servo amplifiers connected by SSCNET
cable.
Motion controller
Device memory
Multiple CPU
high speed
transmission
memory
Q series PLC system bus
PLC intelligent
(DI/O) function module
(A/D, D/A, Network etc.)
(a) The device memory is the memory area for the bit devices (X, Y, M, etc.)
and word devices (D, W, etc.).
(b) The Multiple CPU high speed transmission memory between the PLC CPU
area and Motion CPU area can be communicated at 0.88ms cycles.
Motion CPU area (CPU No.2 fixed)
Device memory
Multiple CPU
high speed
Multiple CPU
bus
high speed
transmission
memory
Motion module
(Proximity dog signal, manual
pulse generator input)
Forced stop input (24VDC)
PERIPHERAL I/F
Personal computer
MT Developer2
2 - 4
Motion control
processor
SSCNET
Servo
amplifier
M Servomotor
M
Servo external
input signals
(FLS, RLS, DOG)