Interrupt Processing; Maskable Interrupt - Intel Quark SoC X1000 Core Developer's Manual

Exceptions are classified as faults, traps, or aborts, depending on the way they are
reported, and whether or not restart of the instruction causing the exception is
supported. Faults are exceptions that are detected and serviced before the execution
of the faulting instruction. A fault would occur in a virtual memory system when the
processor referenced a page or a segment that was not present. The operating system
would fetch the page or segment from disk, and then the Intel
restart the instruction. Traps are exceptions that are reported immediately after the
execution of the instruction that caused the problem. User defined interrupts are
examples of traps. Aborts are exceptions that do not permit the precise location of the
instruction causing the exception to be determined. Aborts are used to report severe
errors, such as a hardware error or illegal values in system tables.
Thus, when an interrupt service routine has been completed, execution proceeds from
the instruction immediately following the interrupted instruction. On the other hand,
the return address from an exception fault routine will always point at the instruction
causing the exception and include any leading instruction prefixes.
summarize the possible interrupts for Intel
the return address points.
®
Intel Quark SoC X1000 Core can handle up to 256 different interrupts and/or
exceptions. In order to service the interrupts, a table with up to 256 interrupt vectors
must be defined. The interrupt vectors are simply pointers to the appropriate interrupt
service routine. In Real Mode (see
are 4-byte quantities, a Code Segment plus a 16-bit offset; in Protected Mode, the
interrupt vectors are 8-byte quantities, which are put in an Interrupt Descriptor Table
(see Section 6.2.3.4, "Interrupt Descriptor Table" on page
interrupts, 32 are reserved for use by Intel, the remaining 224 are free to be used by
the system designer.
3.7.2

Interrupt Processing

When an interrupt occurs, the following actions happen. First, the current program
address and the Flags are saved on the stack to allow resumption of the interrupted
program. Next, an 8-bit vector is supplied to the Intel
appropriate entry in the interrupt table. The table contains the starting address of the
interrupt service routine. Then, the user supplied interrupt service routine is executed.
Finally, when an IRET instruction is executed the old Intel
restored and program execution resumes at the appropriate instruction.
The 8-bit interrupt vector is supplied to the Intel
ways: exceptions supply the interrupt vector internally; software INT instructions
contain or imply the vector; maskable hardware interrupts supply the 8-bit vector via
the interrupt acknowledge bus sequence. Non-maskable hardware interrupts are
assigned to interrupt vector 2.
3.7.3

Maskable Interrupt

Maskable interrupts are the most common way used by the Intel
respond to asynchronous external hardware events. A hardware interrupt occurs when
the INTR is pulled high and the Interrupt Flag bit (IF) is enabled. The Intel
only responds to interrupts between instructions, (REPeat String instructions, have an
"interrupt window," between memory moves, which allows interrupts during long string
moves). When an interrupt occurs, the Intel
supplied by the hardware which identifies the source of the interrupt, (one of 224 user
defined interrupts). The exact nature of the interrupt sequence is discussed in
10.3.10, "Interrupt Acknowledge" on page
®
Intel Quark SoC X1000 Core
Developer's Manual
34
®
Intel Quark Core—Architectural Overview
®
Quark SoC X1000 Core and shows where
Chapter 5.0, "Real Mode
®
Quark Core which identifies the
®
®
Quark Core in several different
®
Quark Core reads an 8-bit vector
219.
®
Quark Core would
Table 5 and Table 6
Architecture"), the vectors
71). Of the 256 possible
Quark Core state is
®
Quark Core to
®
Quark Core
Section
October 2013
Order Number: 329679-001US