Protection And I/O Permission Bitmap - Intel Quark SoC X1000 Core Developer's Manual

Protected Mode Architecture—Intel
The paging hardware allows the 20-bit linear address produced by a Virtual Mode
program to be divided into up to 256 pages. Each one of the pages can be located
anywhere within the maximum 4-Gbyte physical address space of the Intel
SoC X1000 Core. In addition, because CR3 (the Page Directory Base Register) is loaded
by a task switch, each Virtual Mode task can use a different mapping scheme to map
pages to different physical locations. Finally, the paging hardware allows the sharing of
the operating system code between multiple applications.
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Intel Quark SoC X1000 Core paging hardware enables multiple programs to run under
a virtual memory demand paged system.
6.5.4

Protection and I/O Permission Bitmap

All Virtual 8086 Mode programs execute at privilege level 3, the level of least privilege.
As such, Virtual 8086 Mode programs are subject to all of the protection checks defined
in Protected Mode. (This is different from Real Mode, which implicitly is executing at
privilege level 0, the level of greatest privilege.) Thus, an attempt to execute a
privileged instruction when in Virtual 8086 Mode causes an exception 13 fault.
The following are privileged instructions that can be executed only at Privilege Level 0.
Therefore, attempting to execute these instructions in Virtual 8086 Mode (or anytime
CPL > 0) causes an exception 13 fault:
LIDT; MOV DRn,reg; MOV reg,DRn;
LGDT; MOV TRn,reg; MOV reg,TRn;
LMSW; MOV CRn,reg; MOV reg,CRn;
CLTS;
HLT;
Several instructions, particularly those applying to the multi-tasking model and
protection model, are available only in Protected Mode. Therefore, attempting to
execute the following instructions in Real Mode or in Virtual 8086 Mode generates an
exception 6 fault:
LTR; STR;
LLDT; SLDT;
LAR; VERR;
LSL; VERW;
ARPL.
The instructions that are IOPL-sensitive in Protected Mode are:
IN; STI;
OUT; CLI;
INS;
OUTS;
REP INS;
REP OUTS;
In Virtual 8086 Mode, a slightly different set of instructions are made IOPL-sensitive.
The following instructions are IOPL-sensitive in Virtual 8086 Mode:
INT n; STI;
PUSHF; CLI;
POPF; IRET
The PUSHF, POPF, and IRET instructions are IOPL-sensitive in Virtual 8086 Mode only.
This provision allows the IF flag (interrupt enable flag) to be virtualized to the Virtual
8086 Mode program. The INT n software interrupt instruction is also IOPL-sensitive in
Virtual 8086 Mode. Note, however, that the INT 3 (opcode 0CCH), INTO, and BOUND
instructions are not IOPL-sensitive in Virtual 8086 Mode (they are not IOPL sensitive in
Protected Mode either).
October 2013
Order Number: 329679-001US
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Quark Core
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Quark
Figure 48 shows how the
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Intel Quark SoC X1000 Core
Developer's Manual
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