Intel Quark SoC X1000 Core Developer's Manual page 285

Instruction Set Summary—Intel
Table 94. Floating-Point Clock Count Summary (Sheet 3 of 8)
Instruction
CONSTANTS
FLDZ = Load +0.0 Into ST(0)
FLD1 = Load +1.0 Into ST(0)
FLDP1 = Load p Into ST(0)
FLDL2T = Load log2(10) Into ST(0)
FLDL2E = Load log2(e) Into ST(0)
FLDLG2 = Load log10(2) Into ST(0)
FLDLN2 = Load loge(2) Into ST(0)
ARITHMETIC
FADD = Add Real with ST(0)
ST(0)←ST(0) + 32-bit memory
ST(0)←ST(0) + 64-bit memory
ST(d)←ST(0) + ST(i)
FADDP = Add real with ST(0) and Pop (ST(i)← ST(0)
+ST(i))
Notes:
1. If operand is 0 clock counts = 27.
2. If operand is 0 clock counts = 28.
3. If CW.PC indicates 24 bit precision then subtract 38 clocks.
If CW.PC indicates 53 bit precision then subtract 11 clocks.
4. If there is a numeric error pending from a previous instruction, add 17 clocks.
5. If there is a numeric error pending from a previous instruction, add 18 clocks.
6. The INT pin is polled several times while this function is executing to ensure short interrupt latency.
7. If ABS(operand) is greater than π/4 then add n clocks, where n=(operand/(π/4)).
October 2013
Order Number: 329679-001US
®
Quark Core
Format
11011 001 : 1110 1110 :
11011 001 : 1110 1000 :
11011 001 : 1110 1011 :
11011 001 : 1110 1001 :
11011 001 : 1110 1010 :
11011 001 : 1110 1100 :
11011 001 : 1110 1101 :
11011 000 : mod 000 r/m : s-i-b/disp.
11011 100 : mod 000 r/m : s-i-b/disp.
11011 d00 : 11000 ST(i)
11011 110 : 11000 ST(i) :
Cache Hit Concurrent
Penalty
Avg (Lower Execution
if
Range... Avg (Lower
Cache
Upper Range- Upper
Miss
Range)
4
4
8
8
8
8
8
10(8-20) 2
10(8-20) 3
10(8-20)
10(8-20)
®
Intel Quark SoC X1000 Core
Notes
Range)
2
2
2
2
2
7(5-17)
7(5-17)
7(5-17)
7(5-17)
Developer's Manual
285