Encoding Of Integer Instruction Fields; Encoding Of Operand Length (W) Field; Encoding Of The General Register (Reg) Field; Encoding Of Reg Field When The (W) Field Is Not Present In Instruction - Intel Quark SoC X1000 Core Developer's Manual

Instruction Set Summary—Intel
12.2.3

Encoding of Integer Instruction Fields

Within the instruction are several fields that indicate register selection, addressing
mode and so on. The exact encodings of these fields are defined in this section.
12.2.3.1

Encoding of Operand Length (w) Field

For any given instruction that performs a data operation, the instruction executes as a
32-bit operation or a 16-bit operation. Within the constraints of the operation size, the
w field encodes the operand size as either one byte or the full operation size, as shown
in Table 76.
Table 76.

Encoding of Operand Length (w) Field

w Field
0
1
12.2.3.2

Encoding of the General Register (reg) Field

The general register is specified by the reg field, which may appear in the primary
opcode bytes, as the reg field of the "mod r/m" byte, or as the r/m field of the "mod
r/m" byte.
Table 77.

Encoding of reg Field when the (w) Field is Not Present in Instruction

reg Field
October 2013
Order Number: 329679-001US
®
Quark Core
Operand Size during 16-Bit Data
Operations
8 Bits
16 Bits
Register Selected during 16-Bit
Data Operations
000
001
010
011
100
101
110
111
Operand Size during 32-Bit Data
Register Selected during 32-Bit
AX
CX
DX
BX
SP
BP
SI
DI
Operations
8 Bits
32 Bits
Data Operations
EAX
ECX
EDX
EBX
ESP
EBP
ESI
EDI
®
Intel Quark SoC X1000 Core
Developer's Manual
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