Integra DTR-7.8 Service Manual page 170

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -68
Q8501: SII9135CTU (HDMI RECEIVER)
TERMINAL DESCRIPTION(2/4)
Digital Audio Output Pins
Pin Name Pin #
XTALIN 95
XTALOUT 94
MCLK 89
SCK/DCLK 86
WS/DR0 85
SD0/DL0 81
SD1/DR1 82
SD2/DL1 83
SD3/DR2 84
SPDIF/DL2 78
MUTEOUT 75
Differential Signal Data Pins
Pin Name
R0XC+
R0XC-
R0X0+
R0X0-
R0X1+
R0X1-
R0X2+
R0X2-
R1XC+
R1XC-
R1X0+
R1X0-
R1X1+
R1X1-
R1X2+
R1X2-
Strength Type
5V
---
Tolerant
LVTTL
4 mA LVTTL
LVTTL
8 mA
LVTTL
4 mA
LVTTL
4 mA
LVTTL
4 mA
LVTTL
4 mA
LVTTL
4 mA
LVTTL
4 mA
LVTTL
4 mA
LVTTL
4 mA
Type
Pin #
Analog
40
39 Analog
Analog
44
Analog
43
Analog
48
Analog
47
Analog
52
Analog
51
Analog
58
Analog
57
Analog
62
Analog
61
Analog
66
Analog
65
Analog
70
Analog
69
Dir
In
Crystal Clock Input. Also allows LVTTL input.
Frequency required: 26-28.5 MHz
Out
Crystal Clock Output
Out Audio Master Clock Output
Out
I2S Serial Clock Output.
DSD Clock Out.
Out
I2S Word Select Output.
DSD Serial Right Ch0 Data Output
Out
I2S Serial Data Output / DSD Audio Output
Configurable to be shared with DSD.
Out
SD0 = DSD Serial Left Ch0 Data Output
Out
SD1 = DSD Serial Right Ch1 Data Output
Out
SD2 = DSD Serial Left Ch1 Data Output
Out
S/PDIF Audio Output. Configurable to be
shared with DSD
DSD Serial Left Ch2 Data Output
Out
Mute Audio Output. Signal to the external
downstream audio device, audio DAC, etc. to
downstream audio device, audio DAC, etc. to
mute audio output.
TMDS Input Clock Pair
TMDS Input Data Pair
TMDS Input Data Pair
TMDS Input Data Pair
TMDS Input Clock Pair
TMDS Input Data Pair
TMDS Input Data Pair
TMDS Input Data Pair
Description
Description
HDMI Port 0
HDMI Port 1
DTR-7.8