Integra DTR-7.8 Service Manual page 160

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -58
Q8210, Q8510, Q8610: BR24L02FV-W(256x8 bit EEPROM)
BLOCK DIAGRAM AND PIN CONFIGURATION
A0 1
Address
A1 2
Decorder
A2 3
High-voltage
4
GND
generation circuit
TERMINAL DESCRIPTION
Terminal
Vcc
GND
A0,A1,A2
SCL
SDA
WP
2k Bit EEPROM Array
8bit
Slave word
8bit
address register
START STOP
Control circuit
Power voltage
detection
I/O Function
- Apply a power source
- Ground terminal
I Slave address setting terminal
I Serial clock input
Slave and word address.
I/O
Serial data input and output
I Write protect terminal
8
8bit
Data
7
register
6
ACK
5
DTR-7.8
Vcc
WP
SCL
SDA