Dacsbl - Integra DTR-7.8 Service Manual

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -55
Q8801: ADV7172 (Digital PAL/NTSC Video Encoder with six DACs)
BLOCK DIAGRAM
CLOCK PAL NTSC
FIELD/
VIDEO TIMING
GENERATOR
TTX
TELETEXT
INSERTION BLOCK
TTXREQ
V
AA
8
P0
YCrCb
4:2:2 TO
8
TO
4:4:4
COLOR
YUV
INTER-
DATA
MATRIX
POLATOR
P7
8
PIN CONFIGURATION
CLAMP SCLOCK SDATA
2
I C MPU PORT
BRIGHTNESS AND
CONTRAST CONTROL
10
+
ADD SYNC
Y
8
+
INTERPOLATOR
U
10
SATURATION CONTROL
+
8
ADD BURST
10
V +
8
INTERPOLATOR
REAL-TIME
CONTROL CIRCUIT
SCRESET/RTC
48 47 46 45 44 43 42 41 40
1
V
AA
PIN 1
P0 2
IDENTIFIER
P1 3
4
P2
5
P3
ADV7172
P4 6
P5 7
TOP VIEW
8
P6
P7 9
10
CSO_HSO
V 11
AA
GND 12
13 14 15 16 17 18 19 20 21 22 23 24
ALSB
YUV TO
RBG
MATRIX
+
YUV
LEVEL
CONTROL
BLOCK
LUMA
PROGRAMMABLE
FILTER
+
SHARPNESS
FILTER
MODULATOR
PROGRAMMABLE
+
CHROMA
HUE
FILTER
CONTROL
10 10
SIN/COS
DDS BLOCK
GND
39 38 37
36 COMP1
35 DAC A
34 V
AA
DAC B
33
V
32
AA
31
GND
30 V
AA
DAC C
29
DAC D
28
27 V
AA
26 GND
DAC E
25
DTR-7.8
M
10 10
U
10-BIT
DAC A
L
DAC
T
10
I 10
10-BIT
P DAC B
DAC
L
E
10 10
10-BIT
X DAC C
DAC
E
R
V
DAC REF
CONTROL
R
SET2
M
BLOCK
COMP2
U
L
10
10-BIT
T
DAC E
DAC
I
10
P
10
L 10-BIT
10
DAC F
E DAC
X
10 10
E
10-BIT
DAC D
R
DAC
DAC
CONTROL
R
SET1
BLOCK
COMP1