Integra DTR-7.8 Service Manual page 119

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -17
Q3401: D790E001BZDH275/D710E001BZDH275 (Audio DSP)
PIN CONFIGURATION(2/2)
TERMINAL DESCRIPTION(1/5)
SIGNAL NAME
OSCIN
OSCOUT
OSCV
DD
OSCV
SS
CLKIN
PLLHV
RESET
TCK
TMS
TDI
TDO
TRST
EMU[0]
EMU[1]
Core Supply (CV )
DD
IO Supply (DV )
DD
Ground (V )
SS
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 3 5
2 4 6
Bottom View
BALL
(1) (2)
TYPE PULL
NO.
J2 I -
J3 O -
J4 PWR -
J1 PWR -
H2 I -
K2 PWR -
Device Reset
G2 I -
Emulation/JTAG Port
P1 I IPU
K3 I IPU
L1 I IPU
M2 OZ IPU
K4 I IPD
M1 IO IPU
N1 IO IPU
E6, E7, E8, E9, E10, E11, G5, G12, H5, H12, J5, J12, K5, K12, M6, M7, M8, M9, M10, M11
A2, A15, B1, B16, D4, D5, D12, D13, E4, E13, J14, M4, M13, N5, N12, P8, R1, R16, T2, T15
A1, A7, A10, A16, E5, E12, F5, F6, F7, F8, F9, F10, F11, F12, G1, G6, G7, G8, G9, G10, G11, G16, H3,
H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, J10, J11, K1, K6, K7, K8, K9, K10, K11, K16, L5, L6, L7, L8, L9,
L10, L11, L12, M5, M12, T1, T7, T10, T16
7 9 11 13 15
8 10 12 14 16
(3)
GPIO
Clocks
N 1.2-V Oscillator Input
N 1.2-V Oscillator Output
N Oscillator 1.2-V V
N Oscillator V tap point (for filter only)
SS
N Alternate clock input (3.3-V LVCMOS Input)
N PLL 3.3-V Supply Input (requires external filter)
N Device reset pin
N Test Clock
N Test Mode Select
N Test Data In
N Test Data Out
N Test Reset
N Emulation Pin 0
N Emulation Pin 1
Power Pins
DESCRIPTION
tap point (for filter only)
DD
DTR-7.8