Integra DTR-7.8 Service Manual page 154

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -52
Q8001: FLI8125-LF-BC (Video Processor)
TERMINAL DESCRIPTION(8/8)
Parallel/Serial ROM/ SRAM Interface
ROM_OEN
ROM_SDI/
ROM_WEN
ROM_SCSN/
ROM_CSN
Digital Power and Ground
Pin Name
RVDD_3.3
CVDD_1.8
CRVSS
JTAG Boundary Scan
Pin Name
TCK
TDO
TDI
TMS
TRST
118 O External PROM / SRAM data Output Enable.
97 O External PROM / SRAM data Write Enable (for In-System-Programming of FLASH) or Serial
Data Input (SDI) for SPI ROM interface.
94 O External PROM / SRAM data Chip Select or Serial PROM Chip Select (ROM_SCSN) for SPI
ROM interface.
No I/O Description
32 P Ring VDD. Connect to digital 3.3V.
49
98
116
154
18 P Core VDD. Connect to digital 1.8V.
28
39
45
84
119
126
133
143
19 G Chip ground for core and ring.
29
33
40
46
50
85
99
117
120
127
134
144
155
No I/O Description
34 I JTAG Boundary Scan TCK signal
55 O JTAG Boundary Scan TDO signal
35 I JTAG Boundary Scan TDI signal. Pad has internal 50K pull-up resistor.
36 I JTAG Boundary Scan TMS signal. Pad has internal 50K pull-up resistor.
37 I JTAG Boundary Scan RST signal. Pad has internal 50K pull-up resistor.
DTR-7.8