Integra DTR-7.8 Service Manual page 123

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -21
Q3401: D790E001BZDH275/D710E001BZDH275 (Audio DSP)
TERMINAL DESCRIPTION(5/5)
SIGNAL NAME
AHCLKR0/AHCLKR1
ACLKR0
AFSR0
AHCLKX0/AHCLKX2
ACLKX0
AFSX0
AMUTE0
AXR0[0]
AXR0[1]
AXR0[2]
AXR0[3]
AXR0[4]
AXR0[5]/SPI1_SCS
AXR0[6]/SPI1_ENA
AXR0[7]/SPI1_CLK
AXR0[8]/AXR1[5]/
SPI1_SOMI
AXR0[9]/AXR1[4]/
SPI1_SIMO
AXR0[10]/AXR1[3]
AXR0[11]/AXR1[2]
AXR0[12]/AXR1[1]
AXR0[13]/AXR1[0]
AXR0[14]/AXR2[1]
AXR0[15]/AXR2[0]
ACLKR1
AFSR1
AHCLKX1
ACLKX1
AFSX1
AMUTE1
AHCLKR2
ACLKR2
AFSR2
ACLKX2
AFSX2
AMUTE2/HINT
SPI0_SOMI/I2C0_SDA
SPI0_SIMO
SPI0_CLK/I2C0_SCL
SPI0_SCS/I2C1_SCL
SPI0_ENA/I2C1_SDA
BALL
(1) (2)
TYPE PULL
NO.
McASP0, McASP1, McASP2, and SPI1 Serial Ports
B3 IO -
A5 IO -
B4 IO -
C2 IO -
A4 IO -
A3 IO -
C1 O -
A14 IO -
B13 IO -
A13 IO -
B12 IO -
A12 IO -
B11 IO -
A11 IO -
B10 IO -
B9 IO -
A9 IO -
B8 IO -
A8 IO -
B7 IO -
B6 IO -
A6 IO -
B5 IO -
E1 IO -
F1 IO -
D1 IO -
E2 IO -
F2 IO -
D2 O -
C14 IO IPD
C13 IO IPD
C12 IO IPD
D11 IO IPD
C11 IO IPD
D10 O IPD
SPI0, I2C0, and I2C1 Serial Port Pins
B14 IO -
B15 IO -
C16 IO -
C15 IO -
D16 IO -
(3)
GPIO
Y McASP0 and McASP1 Receive Master Clock
Y McASP0 Receive Bit Clock
Y McASP0 Receive Frame Sync (L/R Clock)
Y McASP0 and McASP2 Transmit Master Clock
Y McASP0 Transmit Bit Clock
Y McASP0 Transmit Frame Sync (L/R Clock)
Y McASP0 MUTE Output
Y McASP0 Serial Data 0
Y McASP0 Serial Data 1
Y McASP0 Serial Data 2
Y McASP0 Serial Data 3
Y McASP0 Serial Data 4
Y McASP0 Serial Data 5 or SPI1 Slave Chip Select
Y McASP0 Serial Data 6 or SPI1 Enable (Ready)
Y McASP0 Serial Data 7 or SPI1 Serial Clock
McASP0 Serial Data 8 or McASP1 Serial Data 5 or
Y
SPI1 Data Pin Slave Out Master In
McASP0 Serial Data 9 or McASP1 Serial Data 4 or
Y
SPI1 Data Pin Slave In Master Out
Y McASP0 Serial Data 10 or McASP1 Serial Data 3
Y McASP0 Serial Data 11 or McASP1 Serial Data 2
Y McASP0 Serial Data 12 or McASP1 Serial Data 1
Y McASP0 Serial Data 13 or McASP1 Serial Data 0
Y McASP0 Serial Data 14 or McASP2 Serial Data 1
Y McASP0 Serial Data 15 or McASP2 Serial Data 0
Y McASP1 Receive Bit Clock
Y McASP1 Receive Frame Sync (L/R Clock)
Y McASP1 Transmit Master Clock
Y McASP1 Transmit Bit Clock
Y McASP1 Transmit Frame Sync (L/R Clock)
Y McASP1 MUTE Output
Y McASP2 Receive Master Clock
Y McASP2 Receive Bit Clock
Y McASP2 Receive Frame Sync (L/R Clock)
Y McASP2 Transmit Bit Clock
Y McASP2 Transmit Frame Sync (L/R Clock)
Y McASP2 MUTE Output or UHPI Host Interrupt
Y SPI0 Data Pin Slave Out Master In or I2C0 Serial Data
Y SPI0 Data Pin Slave In Master Out
Y SPI0 Serial Clock or I2C0 Serial Clock
Y SPI0 Slave Chip Select or I2C1 Serial Clock
Y SPI0 Enable (Ready) or I2C1 Serial Data
DTR-7.8
DESCRIPTION