Integra DTR-7.8 Service Manual page 150

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -48
Q8001: FLI8125-LF-BC (Video Processor)
TERMINAL DESCRIPTION(4/8)
Digital Video Input Port
Pin Name
VID_DATA_IN_23
VID_CLK2
VID_DE/FLD
System Interface
Pin Name
RESETn
TEST
GPIO15
JTAG_BS_ENn
SCART16
HOST_SCLK
HOST_SDATA
DDC_SCLK
DDC_SDATA
MSTR_SCLK
MSTR_SDATA
GPIO0/TCK
GPIO1/TDI
GPIO2/TMS
GPIO3/TRST
GPIO6/IRin
GPIO7/IRQin
GPIO8/IRQout
GPIO9/SIPC_SCLK
GPIO10/SIPC_SDATA/
A18
GPIO11/PWM0
GPIO12/PWM1
No I/O Description
132
118 I Video port data clock input meant for Video Input – 2. Up to 135Mhz
[Input, 5V-tolerant]
115 I Video Active Signal Input or the Field Signal Input from external Digital Video Source.
No I/O Description
10 I Hardware Reset (active low) [Schmitt trigger, 5v-tolerant]
Connect to ground with 0.01uF capacitor.
20 I For normal mode of operation connect this Pin to Ground. Has an internal pulldown
resistor of 50 K ohm.
21 IO This pin is available as a general-purpose input/output port. Also it is optionally
programmable to give out the external chip select signal meant for external SRAM.
Connect pullup resistor to supply if external SRAM used. It is also address line A19 when
1MB parallel flash is used.
22 I JTAG Boundary Scan enabling pin. Has an internal pulldown resistor of 50 K ohm.
If this pin is left open or pulled down, Boundary Scan Mode is enabled.
If this pin is pulled high, Boundary Scan functionality is not available, and pins 34~37 are
available as GPIO 0~3
23 I This pin can be programmed to sense the Fast Blank Input signal from a SCART I/P
source
24 IO Host input clock or 186 UART Data In or JTAG clock signal.
[Input, Schmitt trigger, 5V-tolerant]
25 IO Host input data or 186 UART Data Out or JTAG mode signal.
[Bi-directional, Schmitt trigger, slew rate limited, 5V-tolerant]
26 IO DDC2Bi clock for VGA Port
27 IO DDC2Bi data for VGA Port
30 O Clock signal from Master Serial 2 Wire Interface Controller
31 IO Data signal meant for Master Serial 2 Wire interface Controller
34 IO This Pin accepts the Input Clock signal in case of Boundary Scan Mode. Else, this pin is
available as General Purpose Input/output Port.
35 IO This Pin accepts the Input Data signal in case of Boundary Scan Mode. Else, this pin is
available as General Purpose Input/output Port.
36 IO This Pin accepts the Input Test Mode Select signal in case of Boundary Scan Mode. Else,
this pin is available as General Purpose Input/output Port.
37 IO This Pin accepts the Boundary Scan Reset signal in case of Boundary Scan Mode. Else,
this pin is available as General Purpose Input/output Port.
38 IO Input from Infra Red Decoder can be connected to this Pin. Else, this pin is available as
General Purpose Input/output Port.
41 IO Input Interrupt Request signal can be connected to this Pin. Else, this pin is available as
General Purpose Input/output Port.
42 IO This Pin will give out the Interrupt Signal to interrupt external Micro. Else, this pin is
available as General Purpose Input/output Port.
43 IO This Pin accepts the Clock signal from External Serial 2 Wire interface Bus if FLI8125 is
programmed to be in Slave mode. Else, this pin is available as General Purpose
Input/output Port.
44 IO This Pin acts as the Data I/O signal when used with External Serial 2 Wire interface Bus if
FLI8125 is programmed to be in Slave mode. Or this Pin is programmable to give out
Address line 18 from the Internal Micro when used with 512K External Memory. Else, this
pin is available as General Purpose Input/output Port.
47 IO This Pin can be programmed to give out Pulse Width Modulated Output Pulses for
external use. Else, this pin is available as General Purpose Input/output Port.
48 IO This Pin can be programmed to give out Pulse Width Modulated Output Pulses for
external use. Else, this pin is available as General Purpose Input/output Port.
DTR-7.8