Integra DTR-7.8 Service Manual page 138

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -36
Q3651 : ES29LV800ET-70TG (8 Mbit Flash Memory)
BLOCK DIAGRAM
Vcc
Vcc Detector
Vss
Command
#
WE
Register
RESET#
A<0:18>
CE#
Chip Enable
OE#
Output Enable
Logic
BYTE#
RY/BY#
Timer/
Counter
Write
State
Machine
Sector Switches
Analog Bias
Generator
Y-Decoder
X-Decoder
DTR-7.8
DQ0-DQ15(A-1)
Input/Output
Buffers
Data Latch/
Sense Amps
Y-Decoder
Cell Array