General Purpose I/O Header - Supermicro X10SDV User Manual

X10SDV Flex ATX Series Motherboard User's Manual

General Purpose I/O Header

The JGP1 header is a general purpose
I/O on a pin header. See the table on
the right for pin definitions. Refer to the
board layout below for the location of
the header.
GPIO Register Address Table To Control JGPIO Pin Header
JGPIO1 PIN#
1
2
3
4
5
6
7
8
9
10
Note: Please refer to the Intel Xeon Processor D-1500 Product Family
Datasheet for more information.
JI2C1/JI2C2:
JBR1
1-2:ENABLE 1-2:NORMAL
BAR CODE
2-3:DISABLE 2-3:BIOS RECOVERY
JPG1:
1-2:ENABLE
2-3:DISABLE
JPS1:SAS
1-2:ENABLE
2-3:DISABLE
JWD1:WATCH DOG
1-2:RST
2-3:NMI JL1:
CHASSIS
INTRUSION
JOH1-OH
MP_SRW2
JIPMB1
BMC
AST2400
MP_SRW1
JMP1
PCI-E 2.0 X1 / I-SATA5
COM1
JPME2
JLANLED1
JTGLED1
JD1
JOH1
LSI
A
2116
LEDS1
(-7TP4F/-7TP8F)
I-SATA3
JSAS1
L-SAS0-3
JSAS3 JSAS4
L-SAS8-11 L-SAS12-15
I-SATA2 PRESS FIT PRESS FIT
SoC GPIO# USE Select
Power
Ground
17 IO 0x500 [17]
68 IO 0x540 [4]
01 IO 0x500 [1]
69 IO 0x540 [5]
06 IO 0x500 [6]
70 IO 0x540 [6]
07 IO 0x500 [7]
71 IO 0x540 [7]
LED7
A
PRESS FIT
C
UID
VGA
JPL3:
M2_SRW3 LAN3/4/5/6
1-2:ENABLE
2-3:DISABLE
C
LED8
PHY
10GbE
CS2447
A
C
LEDM1
M2_SRW2
A
A
i350 C C
AM4
A A
(-7TP8F/
C C
-TP8F)
JPL1/JPL2:
LAN 7/8 LAN1/
1-2:ENABLE
JPTG1
M2_SRW1
Intel Xeon
JMD1: M.2
PCI-E 3.0 X4 / I-SATA4
D-1500
SoC
JTPM1
PRESS FIT
USB 2
A
PRESS FIT
LED3
FAN4
JF1 JGP1
2-26
Pin# Definition
1 P3V3
3 GP0
5 GP2
7 GP4
9 GP6
IO Select
IO 0x504 [17]
IO 0x544 [4]
IO 0x504 [1]
IO 0x544 [5]
IO x0504 [6]
IO 0x544 [6]
IO 0x504 [7]
IO 0x544 [7]
A. General Purpose Header
IPMI_LAN
LAN 5/6 LAN 3/4
LAN 1/2
USB 0/1(3.0)
JPUSB1
JPV1
LAN2
2-3:DISABLE
JPW1
JBT1:
CMOS
CLEAR
JPH1
BT1
FAN3
JF1:
PWR OH NIC2 HDD PWR
RST X FF NIC1 LED
ON LED
GPIO Header
Pin Definitions
Pin Definition
2 GND
4 GP1
6 GP3
8 GP5
10 GP7
Level
IO 0x50C [17]
IO 0x548 [4]
IO 0x50C [1]
IO 0x548 [5]
IO 0x50C [6]
IO 0x548 [6]
IO 0x50C [7]
IO 0x548 [7]
JPI2C1