Serial Link I/O Header; System Management Bus Header - Supermicro X10SDV User Manual

X10SDV Flex ATX Series Motherboard User's Manual

Serial Link I/O Header

The Serial Link General Purpose In-
put/Output (SGPIO) header is used to
communicate with the enclosure man-
agement chip in the system. See the
table on the right for pin definitions.

System Management Bus Header

The System Management Bus header
for additional slave devices or sensors
is located as JSMB1. Refer to the table
on the right for pin definitions.
JI2C1/JI2C2: JBR1
1-2:ENABLE
1-2:NORMAL BAR CODE
2-3:DISABLE 2-3:BIOS RECOVERY
JPG1:
1-2:ENABLE
2-3:DISABLE
JPS1:SAS
1-2:ENABLE
2-3:DISABLE
JWD1:WATCH DOG
1-2:RST
2-3:NMI JL1: CHASSIS
INTRUSION
JOH1-OH
MP_SRW2
JIPMB1
BMC
AST2400
B
MP_SRW1
JMP1
PCI-E 2.0 X1 / I-SATA5
COM1
JLANLED1
JTGLED1
JOH1
LSI
A
2116
LEDS1
(-7TP4F/-7TP8F)
I-SATA3
JSAS3
L-SAS8-11
I-SATA2 PRESS FIT
LED7
A
C
UID
VGA
M2_SRW3
C
LED8
PHY
10GbE
CS2447
A
C
LEDM1
M2_SRW2
i350
AM4
(-7TP8F/
-TP8F)
JPTG1
M2_SRW1
JPME2
JMD1: M.2
PCI-E 3.0 X4 / I-SATA4
JD1
JTPM1
PRESS FIT
USB 2
JSAS1
L-SAS0-3
JSAS4
L-SAS12-15
PRESS FIT
PRESS FIT
FAN4
Serial Link I/O Header
Pin# Definition
1 NC
3 Ground
5 Load
7 Clock
SMBus Power
Pin Definitions
Pin# Definition
1 Data
2 Ground
3 Clock
A. I-SGPIO1
B. JSMB1
PRESS FIT
JPL3:
LAN3/4/5/6
1-2:ENABLE
2-3:DISABLE
LAN 5/6 LAN 3/4
A A
C C
A A
C C
JPL1/JPL2:
LAN 7/8 LAN1/ LAN2
1-2:ENABLE 2-3:DISABLE
Intel Xeon
D-1500
SoC
JBT1:
CMOS
CLEAR
A
BT1
FAN3
LED3
JF1 JGP1
PWR
RST X FF
ON
2-24
Pin Definitions
Pin Definition
2 NC
4 DATA Out
6 Ground
8 NC
IPMI_LAN
LAN 1/2
USB 0/1(3.0)
JPUSB1
JPV1
JPI2C1
JPW1
JPH1
JF1:
OH NIC2 HDD PWR
NIC1 LED
LED