Samsung OFFICESERV 7100 Service Manual page 108

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3.3.1.3 PLL Operation is Abnormal
The procedure for resolving the problem caused by Phase Locking Loop(PLL) operation is
as follows:
Start
Is REFERENCE
clock selection MMC selected?
Yes
Is the REFERENCE
clock normal?
Yes
Is 2 kHz norma?
Yes
Is DUTY of FOI signal steady?
Yes
Check if the corresponding channel
signal of highway TX is generated.
If PLL fails, a call can be connected but there is noise while calling.
3-14
No
Set the REFERENCE clock.
Check the REFERENCE clock of
No
TEPRI board, main board and
MP10/11 board.
No
- MP10/11: Check PINT2 of U22.
- If REFERENCE clock sometimes
shakes, TEPRI line is abnormal.
No
- If REFERENCE clock does not
shake, repair the VCO circuit.
MP10/11: Composed of U23, U24,
and Y1.
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