Overview; Feature Summary - Intel D815EEA Technical Product Specification

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Intel Desktop Board D815EEA Technical Product Specification

1.1 Overview

1.1.1 Feature Summary

Table 1 summarizes the D815EEA board's major features.
Table 1.

Feature Summary

Form Factor
Processor
Memory
Chipset
I/O Control
Video
Peripheral
Interfaces
Expansion
Capabilities
BIOS
Diagnostic LEDs
Instantly Available
PC
†
Wake on LAN
Technology
Connector
For information about
The board's compliance level with APM, ACPI, Plug and Play, and SMBIOS.
12
ATX (12.0 inches by 8.2 inches)
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Support for either an Intel
(FC-PGA) package or an Intel
PPGA package
• Three 168-pin SDRAM Dual Inline Memory Module (DIMM) sockets
• Support for up to 512 MB system memory
• Single- or double-sided DIMMs supported
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Intel 815E Chipset, consisting of:
• Intel
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82815E Graphics and Memory Controller Hub (GMCH)
• Intel
®
82801BA I/O Controller Hub (ICH2)
• Intel
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82802AB 4 Mbit Firmware Hub (FWH)
SMSC LPC47M102 LPC bus I/O controller
• Intel
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82815E integrated graphics support
• AGP universal connector supporting 1X, 2X, and 4X AGP cards or a Graphics
Performance Accelerator (GPA)
• Digital video output (DVO) connector
• Four Universal Serial Bus (USB) ports
• Two serial ports
• One parallel port
• Two IDE interfaces with Ultra DMA, ATA-66/100 support
• One diskette drive interface
• MIDI/game port
• PS/2
†
keyboard and mouse ports
• Five PCI bus add-in card connectors (SMBus routed to PCI bus connector 2)
• One AGP universal connector
• Intel/AMI BIOS (resident in the Intel 82802AB 4 Mbit FWH)
• Support for Advanced Power Management (APM), Advanced Configuration and
Power Interface (ACPI), Plug and Play, and SMBIOS
Four dual-color LEDs on back panel
• Support for PCI Local Bus Specification Revision 2.2
• Suspend to RAM support
• Wake on PS/2 keyboard and USB ports
Support for system wake up using an add-in network interface card with remote
wake up capability
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Pentium III processor in a Flip Chip Pin Grid Array
® ™
Celeron processor in an FCPGA package or a
Refer to
Section 1.3, page 16