Chipset Configuration; North Bridge; Integrated Io Configuration - Supermicro X10QBL-CT User Manual

Chipset Configuration
North Bridge
This feature is used to configure Intel North Bridge settings.
Integrated IO Configuration
EV DFX (Device Function On-Hide) Features
When this feature is set to Enable, the EV_DFX Lock Bits that are located
inside a processor will always remain clear during electric tuning. The options
are Disable and Enable.
IIO0 Configuration
CPU1 SLOT1 PCI-E 3.0 X16
Use the items below to configure the PCI-E settings for a PCI-E port specified
by the user.
The following items will display:
•
PCI-E Port Link Status
•
PCI-E Port Link Max
•
PCI-E Port Link Speed
Link Speed
Use this item to select the PCI-E link speed for the PCI-E port specified by the
user. The options are Auto, GEN1 (2.5 GT/s), GEN2 (5 GT/s), and GEN3 (8
GT/s).
PCI-E ASPM Support
Select Enable to support the Active State Power Management (ASPM) level for
a PCI-E port specified by the user. Select Disabled to disable ASPM support.
The options are Auto, Disable, and L1 Only.
4-11
Chapter 4: AMI BIOS