Introduction; Primary Differences; Brefclk; Table D-1: Brefclk Differences Summary - Xilinx RocketIO X User Manual

R
Virtex-II Pro to Virtex-II Pro X FPGA
Design Migration

Introduction

This appendix describes important differences regarding migration from Virtex-II Pro™ to
the Virtex-II Pro™ X FPGAs. Note that this appendix does not describe all of the features
and capabilities of these devices, but only highlights relevant PCB, power supply, and
reference clock differences. For more information on Virtex-II Pro and Virtex-II Pro X
FPGAs, refer to the Virtex-II Pro Data Sheet (

Primary Differences

Virtex-II Pro X FPGAs are pin compatible with corresponding Virtex-II Pro family
members. The primary differences between Virtex-II Pro and Virtex-II Pro X FPGAs are:
•
•

BREFCLK

As with Virtex-II Pro FPGAs, at speeds of 2.5 Gb/s or greater, the REFCLK configuration
introduces more than the maximum allowable jitter to the RocketIO X transceiver. For this
reason, the BREFCLK configuration is required.
The BREFCLK configuration uses dedicated routing resources that reduce jitter. BREFCLK
differences between Virtex-II Pro and Virtex-II Pro X FPGAs are summarized in

Table D-1: BREFCLK Differences Summary

Differences
BREFCLK Inputs
Reference Frequency
Termination
BREFCLK Selection
BREFCLK must enter the FPGA through dedicated differential clock I/O. This BREFCLK
can connect to the BREFCLK input of the transceiver and the CLKIN input of the DCM for
creation of USRCLKs. If transceivers on both the top and bottom of the FPGA are to be
used, two BREFCLKs must be created: one for the top of the chip and one for the bottom.
These dedicated clocks use the same clock inputs for all packages, as shown in
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
BREFCLK - High-speed, lower jitter upgrade supporting up to 10.3125 Gb/s I/O
Multi-Gigabit Transceiver (MGT) - supporting 2.488 Gb/s to 10.3125 Gb/s I/O
Virtex-II Pro FPGAs
2 top, 2 bottom
Up to 156.25 MHz
On-chip or Off-chip 100Ω Differential
Attribute (REF_CLK_V_SEL) and Port (REFCLKSEL)
) and the RocketIO User Guide (
DS083
www.xilinx.com
1-800-255-7778
Appendix D
UG024
Table
Virtex-II Pro X FPGAs
1 top, 1 bottom
Up to 645 MHz
On-chip 100Ω Differential
Port (REFCLKBSEL)
Table
).
D-1.
D-2.
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