Page 1 ® ® 89HPEB383 ® PCI Express Bridge User Manual July 2011 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2011 Integrated Device Technology, Inc.
Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.
Page 3: Table Of Contents
Contents About this Document........... . . 1 Scope .
Page 4 Contents Prefetchable Space............... . . 31 I/O Space .
Page 5 Contents PCI Arbitration Scheme ..............60 Interrupt Handling .
Page 6 Contents 11.3.7 LDn State ............... . 95 11.3.8 Link State Summary .
Page 7 Contents 14.3.13 PCI Bridge Control and Interrupt Register ..........139 14.3.14 Secondary Retry Count Register .
Page 8 Contents 14.8.6 PCIe Correctable Error Mask Register ..........193 14.8.7 PCIe Advanced Error Capabilities and Control Register .
Page 9 Contents 16. Packaging ............235 16.1 Pinouts and Mechanical Diagrams.
Page 10 viii Contents PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 11 Figures Figure 1: PEB383 Block Diagram ..............6 Figure 2: PEB383 Device Architecture .
Page 12 Figures Figure 43: Input Timing Measurement Waveforms ............232 Figure 44: Output Timing Measurement Waveforms .
Page 13 Tables Table 1: Pin Types ................. 13 Table 2: PCIe Interface Signals .
Page 14 Tables Table 43: PEB383 Power Dissipation ..............220 Table 44: PEB383 Power Dissipation per Supply .
Page 15: About This Document
About this Document This section discusses the following topics: • “Scope” on page 1 • “Document Conventions” on page 1 Scope The PEB383 User Manual discusses the features, configuration requirements, and design architecture of the PEB383. Document Conventions This document uses the following conventions. Non-differential Signal Notation Non-differential signals are either active-low or active-high.
Page 16 About this Document Object Size Notation • A byte is an 8-bit object. • A word is a 16-bit object. • A doubleword (Dword) is a 32-bit object. Numeric Notation • Hexadecimal numbers are denoted by the prefix 0x (for example, 0x04). •...
Page 17: Revision History
About this Document Revision History October 22, 2009: Initial publication of PEB383 User Manual. November 18, 2009: Updated pinouts for QFN and QFP packages. December 8, 2009: Updated pinouts and package drawings for QFN and QFP packages. December 18, 2009: Added simulated power numbers to Table 43. Updated Tables 51 and 52 with simulated Thermal Characteristics values.
Page 18 About this Document PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 19: Functional Overview
• “Typical Applications” Overview The IDT PEB383 is a high-performance bus bridge that connects the PCI Express (PCIe) protocol to the PCI bus standard (see Figure The PEB383’s PCIe Interface supports a x1 lane PCIe configuration. This enables the bridge to offer exceptional throughput performance of up to 2.5 Gbps per transmit and receive direction.
Page 20: Features
1. Functional Overview > Features Figure 1: PEB383 Block Diagram Features The PEB383’s key features are listed in the following sub-sections. 1.2.1 General Features • Forward bridge, PCIe to PCI • Single store and forward for optimal latency performance • Supports two modes of addressing: —...
Page 21: Pcie Features
1. Functional Overview > Features • 3.3V PCI I/Os with 5V tolerant I/Os • Support for four external PCI bus masters through an integrated arbiter • Support for external PCI bus arbiter • Support for Masquerade mode (can overwrite vendor and device ID from EEPROM) •...
Page 22: Device Architecture
1. Functional Overview > Device Architecture Device Architecture A high-level, architectural diagram of the PEB383 is displayed in Figure 2. For more information about data flow through the device, see “Upstream Data Path” “Downstream Data Path”. Figure 2: PEB383 Device Architecture PC Ie (Pri mary In terface) Rx PHY Tx PHY...
Page 23 1. Functional Overview > Device Architecture PCI data that is destined for the PCIe fabric are subject to PCIe ordering rules. Data is pulled from the appropriate queue: • Configuration register • Upstream posted write buffer • Upstream read request queue •...
Page 24: Typical Applications
1. Functional Overview > Typical Applications A read initiated on the PCI bus that is decoded for an upstream target is handled as a delayed transaction by the PEB383. The bridge latches the read transaction and attempts to reserve buffer space in its upstream read completion buffer.
Page 25: Figure 4: Dvr Card Application
1. Functional Overview > Typical Applications Figure 4: DVR Card Application Camera Camera Camera Camera Video Video Video Video Decoder Decoder Decoder Decoder PCI Bus PEB383 80E2000_TA002_01 x1 PCIe Figure 5: Motherboard Application PCI Slot PCI Slot 10x10 mm footprint PEB383 Supports up to four PCI devices off x1 PCIe...
Page 26: Figure 6: Expresscard Application
1. Functional Overview > Typical Applications Figure 6: ExpressCard Application x1 PCIe PEB383 I/O Controller 80E2010_TA001_01 PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 27: Signal Descriptions
Signal Descriptions Topics discussed include the following: • “Overview” • “PCIe Interface Signals” • “PCI Interface Signals” • “EEPROM Interface Signals” • “JTAG Interface Signals” • “Power-up Signals” • “Power Supply Signals” Overview Signals are classified according to the types defined in the following table. Table 1: Pin Types Pin Type Definition...
Page 28: Pcie Interface Signals
2. Signal Descriptions > PCIe Interface Signals Table 1: Pin Types (Continued) Pin Type Definition PCIE Diff Out PCIe differential output PCIE Diff In PCIe differential input PCIe Interface Signals Table 2: PCIe Interface Signals Name Pin Type Description Design Recommendation PCIE_PERSTn 3.3 In Master reset in:...
Page 29: Pci Interface Signals
PCI_CLKO[4:0] signals (see “Clocking”). PCI_CLKO[4:0] PCI Out PCI Output Clocks Point-to-point connection to PCI device. IDT recommends a 33 Ohm series (see “Clocking”). termination resistor. In Master clocking mode, PCI_CLKO[4] should be connected to PCI_CLK. PCI_DEVSELn PCI Bidir Device Select.
Page 30 2. Signal Descriptions > PCI Interface Signals Table 3: PCI Interface Signals (Continued) Name Pin Type Description Design Recommendation PCI_GNTn[3:0] PCI Bidir / PCI Bus Grant. The PEB383 uses these PCI_GNTn[3:0] outputs connect directly multifunction signals to grant access to to the PCI device’s PCI_GNTn inputs.
Page 31 2. Signal Descriptions > PCI Interface Signals Table 3: PCI Interface Signals (Continued) Name Pin Type Description Design Recommendation PCI_M66EN PCI In 66-MHz Enable. This signal enables the PCI_M66EN is used only in master PCI Interface for 66-MHz operation. clocking mode. 0 = 33-MHz operation Embedded designs 1 = 66-MHz operation...
Page 32: Eeprom Interface Signals
2. Signal Descriptions > EEPROM Interface Signals Table 3: PCI Interface Signals (Continued) Name Pin Type Description Design Recommendation PCI_RSTn PCI Out PCI reset: This signal resets all devices No pull-up or pull-down resistor is on the PC bus. required. PCI_SERRn PCI Bidir OD System Error.
Page 33: Jtag Interface Signals
2. Signal Descriptions > JTAG Interface Signals JTAG Interface Signals Table 5: JTAG Interface Signals Name Pin Type Description Design Recommendation JTAG_TCK 3.3 In Test Clock. This signal clocks state Connect to 3.3V using a 2K pull-up information and data into and out of the resistor.
Page 34: Power Supply Signals
2. Signal Descriptions > Power Supply Signals Power Supply Signals Table 7: Power Supply Signals Name Pin Type Description Design Recommendation Core power 1.05V core power None. VDD_PCI I/O power 3.3 volt I/O power for PCI and 3.3V I/O None. power for CMOS VDD_PCIE Core power...
Page 35: Data Path
Data Path Topics discussed include the following: • “Overview” • “Transaction Management” • “Buffer Structure” • “Flow Control” • “Prefetching Algorithm” • “Short Term Caching” • “Polarity Inversion” Overview The PEB383 uses two buffering methods for transferring data between its PCIe and PCI ports: •...
Page 36: Downstream Data Path
3. Data Path > Overview Figure 7: Upstream Data Path[update for PEB383] Stage Buffering Device Core Stage Bufferi n g Store and Forward Interface Cu t throu gh Address Decoder Posted FIFO R etry Bu ffer (1 KB) Posted Buffer (512 bytes) ( 512 by tes) Posted Request Cl a im...
Page 37: Transaction Management
3. Data Path > Transaction Management Figure 8: Downstream Data Path Devi ce Core Interface Receive Flow Contr ol B uffer s Posted Buf fer (512 Bytes ) A ddress Packet D ecod er Decoder Non-Posted Queue i t e 4 Entries ECRC Reques t...
Page 38: Downstream Transaction Management
3. Data Path > Buffer Structure The Data link layer applies a sequence number to the TLP received from transaction layer block, and then calculates and appends a 32-bit LCRC value to ensure integrity during the transmission across the physical lanes. A copy of the TLP sent to the physical layer is stored in the retry buffer for future replay if there is negative acknowledgement from the other end component.
Page 39: Upstream Posted Buffer
3. Data Path > Buffer Structure By default the programed allocation amount of buffers that are allocated is equal to the prefetch size. In order to prevent one device from consuming all the buffers, the allocation size can be programmed to be less than the prefetch size.
Page 40: Downstream Non-Posted Buffer
3. Data Path > Flow Control Memory write transactions can contain any or all invalid payload bytes, where as memory write and invalidate (MWI) transactions carry all the valid payload bytes. The PEB383 decomposes the received transactions with non-contiguous byte enables on 32-byte boundaries while writing into the request FIFO.
Page 41: Prefetching Algorithm
3. Data Path > Prefetching Algorithm The PEB383 uses flow control buffers in the PCI Core for three categories of downstream traffic. The amount of flow control buffer space availability is conveyed to the other end of the component using flow control credits.
Page 42: Short Term Caching
3. Data Path > Short Term Caching Short Term Caching This feature provides performance improvements in situations where upstream devices are not able to stream data continuously to meet the prefetching needs of the PEB383. As defined in the PCI-to-PCI Bridge Specification (Revision 1.2), when the bus master completes a transaction, the bridge is required to discard the balance of any data that was prefetched for the master.
Page 43: Addressing
Addressing Topics discussed include the following: • “Overview” • “Memory-mapped I/O Space” • “Prefetchable Space” • “I/O Space” • “VGA Addressing” • “ISA Addressing” • “Non-transparent Addressing” • “Legacy Mode” Overview This chapter discusses the various types of address decoding performed by the PEB383 when it forwards transactions upstream and downstream.
Page 44: Figure 9: Memory-Mapped I/O Address Space
4. Addressing > Memory-mapped I/O Space The response of the bridge to memory-mapped I/O transactions is controlled by the following: • MS bit in “PCI Control and Status Register” – This bit must be set to allow memory transactions to be forwarded downstream.
Page 45: Prefetchable Space
4. Addressing > Prefetchable Space The memory-mapped I/O address range that is defined by the Base and Limit registers are always aligned to a 1-MB boundary and has a size granularity of 1 MB. Prefetchable Space The prefetchable address space maps memory address ranges of devices that are prefetchable; that is, devices that do not have side-effects during reads.
Page 46: I/O Space
4. Addressing > I/O Space Figure 10: 64-bit Prefetchable Memory Address Range Upstream Upstream Downstream Downstream Secondary Interface Secondary Interface Primary Interface Primary Interface Prefetchable Memory Prefetchable Memory 4 GB Boundary 4 GB Boundary 4 GB Boundary 4 GB Boundary Memory Mapped I/O Memory Mapped I/O I/O Space...
Page 47 4. Addressing > I/O Space The Bus Master Enable bit must be set for any I/O transaction to be forwarded upstream. If this bit is not set, all I/O transactions on the PCI bus are ignored. If ISA Enable bit is set, the bridge does not forward any I/O transactions downstream that are in the top 768 bytes of each 1-KB block within the first 64 KB of address space.
Page 48: Vga Addressing
4. Addressing > VGA Addressing Figure 11: I/O Address Space Upstream Upstream Downstream Downstream Primary Interface Primary Interface Secondary Interface Secondary Interface 0x0_C000 – 0x0_FFFF 0x0_C000 – 0x0_FFFF 0x0_B000 – 0x0_BFFF 0x0_B000 – 0x0_BFFF 0x0_A000 – 0x0_AFFF 0x0_A000 – 0x0_AFFF 0x0_9000 –...
Page 49: Isa Addressing
4. Addressing > ISA Addressing VGA I/O Addresses (Address bits 15:10 are not decoded when the VGA 16-Bit Decode bit is 0b) are: • Address bits 9:0 = 0x3B0 through 0x3BB and 0x3C0 through 0x3DF (VGA 16-Bit Decode bit is •...
Page 50: Figure 12: Isa Mode I/O Addressing
4. Addressing > ISA Addressing Figure 12: ISA Mode I/O Addressing Upstream Upstream Downstream Downstream Primary Interface Primary Interface Secondary Interface Secondary Interface 0x0_xD000 – 0x0_xFFF 0x0_xD000 – 0x0_xFFF 0x0_xC00 – 0x0_xCFF 0x0_xC00 – 0x0_xCFF 0x0_x900 – 0x0_x9FF 0x0_x900 – 0x0_x9FF 0x0_x800 –...
Page 51: Non-Transparent Addressing
4. Addressing > Non-transparent Addressing Non-transparent Addressing At power-up, the host processor discovers the need for non-transparent bridging and enables the address remapping of prefetchable, non-prefetchable, and I/O ranges through configuration. Before enabling address remapping of the base and limit values, the remapped address ranges need to be programmed.
Page 52: Pci To Pcie Address Remapping
4. Addressing > Non-transparent Addressing • SecPFAddr = PriPFAddr - PriSecPFDiff, where — SecPFAddr: Defines the remapped address the PEB383 presents on PCI bus. — PriPFAddr: Defines the address presented to the PEB383 that falls within the registers described in the previous paragraph. —...
Page 53 4. Addressing > Non-transparent Addressing The NTMA Secondary Base (see “NTMA Secondary Lower Base Register” “NTMA Secondary Upper Base Register”) and NTMA Secondary Limit (see “NTMA Secondary Lower Limit Register” “NTMA Secondary Upper Limit Register”) define memory windows in the PCI bus memory space that are mapped to arbitrary positions on the PCIe link.
Page 54: Figure 13: Memory Window Remapping Example
4. Addressing > Non-transparent Addressing Figure 13: Memory Window Remapping Example PCIe Address Space PCI Address Space C_FFFF_FFFF 1_FFFF_FFFF Prefetchable Window NTMA Window C000_0000 C_C000_0000 A_FFFF_FFFF 7FFF_FFFF Prefetchable Window NTMA Window 9_C00_0000 4000_0000 3FFF_FFFF BFFF_FFFF Non-prefetchable Window Non-prefetchable Window 0000_0000 8000_0000 I/O Address Remapping “PCI I/O Address Upper 16 Register”...
Page 55: Legacy Mode
4. Addressing > Legacy Mode Legacy Mode When the PEB383 is in Legacy mode it supports subtractive decode. This is a non-standard feature that is enabled through the LEGACY bit in the “PCI Miscellaneous Clock Straps Register”. When the PEB383 is in legacy mode, all MWr, MRd, IOWr, and IORd transactions received on the upstream port (PCIe) that do not decode to an internal address are forwarded to the PCI Interface.
Page 56 4. Addressing > Legacy Mode PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 57: Configuration Transactions
Configuration Transactions Topics discussed include the following: • “Overview” • “Configuration Transactions” • “PCIe Enhanced Configuration Mechanism” • “Configuration Retry Mechanisms” Overview Each device in a PCIe or PCI system has a configuration space that is accessed using configuration transactions in order to define its operational characteristics. This chapter describes how the PEB383 handles PCIe configuration requests.
Page 58: Type 0 Configuration Transactions
5. Configuration Transactions > Configuration Transactions Figure 15: PCI Type 0 Configuration Address Format Unique Address (AD[31:16]) Unique Address (AD[31:16]) Reserved Reserved Function Function Register Register corresponding to a particular Device corresponding to a particular Device Number Number Number Number Number) Number) Figure 16: PCI Type 1 Configuration Address Format...
Page 59: Type 1 To Type 0 Conversion
5. Configuration Transactions > Configuration Transactions If a Type 1 configuration transaction is received on the PCIe Interface, the following sequence of tests is completed on the Bus Number field to determine how the PEB383 should handle the transaction: 1. If the Bus Number field is equal to the Secondary Bus Number value and the conditions for converting the transaction into a Special Cycle transaction are met, the PEB383 forwards the configuration request to its PCI Interface as a Special Cycle transaction.
Page 60: Type 1 To Special Cycle Forwarding
5. Configuration Transactions > PCIe Enhanced Configuration Mechanism To translate the forwarded transaction from a PCIe Type 1 configuration request to a PCI Type 1 configuration transaction, the PEB383 does the following: • Sets address bits PCI_AD[1:0] as 0b01 • PCI Register Number, Function Number, Device Number, and Bus Number (address bits PCI_AD[23:2]) are generated directly –...
Page 61: Configuration Retry Mechanisms
5. Configuration Transactions > Configuration Retry Mechanisms Configuration Retry Mechanisms A PCIe-to-PCI bridge is required to return a completion for all configuration requests that cross the bridge from PCIe to PCI prior to expiration of the Completion Timeout timer in the Root Complex. This requires that bridges take ownership of all configuration requests forwarded across the bridge.
Page 62 5. Configuration Transactions > Configuration Retry Mechanisms PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 63: Bridging
Bridging Topics discussed include the following: • “Overview” • “Flow Control Advertisements” • “Buffer Size and Management” • “Assignment of Requestor ID and Tag” • “Forwarding of PCIe to PCI” • “Forwarding of PCI to PCIe” • “PCI Transaction Support” •...
Page 64: Buffer Size And Management
6. Bridging > Buffer Size and Management Buffer Size and Management The PEB383 provides sufficient buffering to satisfy PCIe bridging requirements. The PEB383 does not overcommit its buffers: it forwards requests onto the other side only when enough buffer space is reserved to handle the returned completions.
Page 65: Forwarding Of Pci To Pcie
6. Bridging > Forwarding of PCI to PCIe • Memory Read Line if the PCIe Request falls into the prefetchable range defined by the “PCI PFM Base and Limit Register”, and the requested data size is less than or equal to the value specified in Cacheline Size of the “PCI Miscellaneous 0 Register”.
Page 66: Pci Non-Posted Requests
6. Bridging > Forwarding of PCI to PCIe 6.6.2 PCI Non-posted Requests The PEB383 processes all non-posted transactions as delayed transactions. The PEB383 first terminates the received non-posted transaction with retry and then forwards it onto the PCIe Interface. The PEB383 stores the request-related state information while forwarding the request onto the PCIe Interface.
Page 67: Pci Transaction Support
6. Bridging > PCI Transaction Support PCI Transaction Support The following table lists the transactions supported by the PCI Interface. Table 10: PCI Transaction Support PCI Interface Transaction As a Master As a Target 0000b Interrupt Acknowledge 0001b Special Cycle 0010b I/O Read 0011b...
Page 68: Pcie Transaction Support
6. Bridging > PCIe Transaction Support PCIe Transaction Support The following table lists the transactions supported by the PCIe Interface. Table 11: PCIe Transaction Support PCIe Interface TLP Type Transaction As a Transmitter As a Receiver Memory Read Request MRdLk Memory Read Request Locked Memory Write Request IORd...
Page 69: Message Transactions
6. Bridging > Message Transactions Message Transactions Message transactions are used for in-band communication of events, and therefore, eliminate the need for sideband signals. PCIe messages are routed depending on specific bit field encodings in the message request header. 6.9.1 INTx Interrupt Signaling The PEB383 forwards the INTx interrupts –...
Page 70: Transaction Ordering
6. Bridging > Transaction Ordering 6.10 Transaction Ordering Table 12 defines the transaction ordering rules that are followed by the PEB383. These rules apply uniformly to all types of transactions, including Memory, I/O, Configurations, and Messages. In the table, the columns represent a first received transaction while the rows represent a subsequently received transaction.
Page 71: Exclusive Access
6. Bridging > Exclusive Access 6.11 Exclusive Access ThePEB383 provides an exclusive access method, which allows non-exclusive accesses to proceed while exclusive accesses take place. This allows a master to hold a hardware lock across several accesses without interfering with non-exclusive data transfer. Locked transaction sequences are generated by the host processor(s) as one or more reads followed by a number of writes to the same location(s).
Page 72 6. Bridging > Exclusive Access PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 73: Pci Arbitration
PCI Arbitration Topics discussed include the following: • “Overview” • “Block Diagram” • “PCI Arbitration Scheme” Overview The PCI internal bus arbiter manages access to the PCI bus for up to five requesters, including the PEB383. The bus arbiter has the following features: •...
Page 74: Pci Arbitration Scheme
7. PCI Arbitration > PCI Arbitration Scheme PCI Arbitration Scheme The arbiter can be programmed to enable or disable, and prioritize, each requester using the “PCI Miscellaneous Control and Status Register”. The PEB383, by default, is assigned a high priority and the other requesters are assigned a low priority. Based on the priority setting, requesters are divided into two groups of high and low priority.
Page 75: Figure 19: Arbitration Pointers - Example 1
7. PCI Arbitration > PCI Arbitration Scheme This is shown conceptually in Figure 19. Here the last served high priority device is H1, and the last served low priority device is L2. When the high priority pointer is at H1, the order of priority is H2, H3, Low, H-PEB383, H0, and H1.
Page 76 7. PCI Arbitration > PCI Arbitration Scheme PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 77: Interrupt Handling
Interrupt Handling Topics discussed include the following: • “Overview” • “Interrupt Sources” • “Interrupt Routing” Overview The PEB383 supports the two types of interrupts that originate on a PCI bus: • Legacy PCI interrupts, PCI_INT[D:A]n • Message-based interrupts — Message Signaled Interrupts (MSI) —...
Page 78: Interrupt Sources
8. Interrupt Handling > Interrupt Sources The Interrupt Message Generation module connects to the PCI Target Interface, external PCI_INT[D:A]n interrupts, and the upstream posted buffer (see Figure 21). Assertion and de-assertion of interrupts are stored in the form of Assert_INTx and Deassert_INTx flags. These flags are kept asserted until the posted buffer can handle corresponding assert and de-assert messages.
Page 79: Error Handling
Error Handling Topics discussed include the following: • “Overview” • “PCIe as Originating Interface” • “PCI as Originating Interface” • “Timeout Errors” • “Other Errors” • “Error Handling Tables” Overview This chapter discusses how the PEB383 handles errors that occur during the processing of upstream and downstream transactions.
Page 80 9. Error Handling > Overview ERR_NONFATAL messages are enabled for transmission if either of the following bits is set: SERR_EN in “PCI Control and Status Register”, or NFTL_ERR_EN in “PCIe Device Control and Status Register”. ERR_COR messages are enabled for transmission if COR_ERR_EN is set in “PCIe Device Control and Status Register”.
Page 81: Figure 22: Pcie Flowchart Of Device Error Signaling And Logging Operations
9. Error Handling > Overview Figure 22: PCIe Flowchart of Device Error Signaling and Logging Operations Integrated Device Technology, Inc. PEB383 User Manual Confidential - NDA Required July 25, 2011...
Page 82: Pcie As Originating Interface
9. Error Handling > PCIe as Originating Interface PCIe as Originating Interface This section describes how the PEB383 handles error support for transactions that flow downstream from PCIe to PCI (see Figure 23). In the case of reception of a Write Request or Read Completion with a Poisoned TLP, the entire data payload of the PCIe transaction is considered as corrupt and the parity is inverted on every data phase forwarded (see Table...
Page 83: Received Poisoned Tlps
9. Error Handling > PCIe as Originating Interface Table 14: Bridge Requirements for Transactions Requiring a Completion (Immediate Response) Immediate PCI Termination PCIe Completion Status Master-Abort Unsupported Request Target-Abort Completer Abort In the case of an Advisory Non-Fatal Error detection, the following actions are taken by the PEB383: 1.
Page 84: Received Ecrc Errors
9. Error Handling > PCIe as Originating Interface 3. If it is not an AFNE then: • Fatal error message is generated if PTLP Mask bit is clear in the “PCIe Uncorrectable Error Mask Register” and either SERR_EN bit is set in “PCI Control and Status Register”...
Page 85: Pci Uncorrectable Data Errors
9. Error Handling > PCIe as Originating Interface 9.2.3 PCI Uncorrectable Data Errors This section describes the bridge requirements for error handling when forwarding downstream a.non-poisoned PCIe transaction to PCI and the bridge detects an uncorrectable data error. The error is detected on the PCI Interface.
Page 86: Pci Uncorrectable Address/Attribute Errors
9. Error Handling > PCIe as Originating Interface 4. Header is logged in the “PCIe Secondary Header Log 1 Register” and the SUFEP field is updated in the “PCIe Secondary Error Capabilities and Control Register” if PERR_AD Mask bit is clear in “PCIe Secondary Uncorrectable Error Mask Register”...
Page 87: Received Master-Abort On Pci Interface
9. Error Handling > PCIe as Originating Interface 5. Error Fatal or Non-Fatal message is generated on PCIe as per the severity level of SERR_AD bit in “PCIe Secondary Uncorrectable Error Severity Register” if SERR_AD Mask bit is clear in “PCIe Secondary Uncorrectable Error Mask Register”...
Page 88: Received Target-Abort On Pci Interface
9. Error Handling > PCIe as Originating Interface 4. Header is logged in the “PCIe Secondary Header Log 4 Register” and ERR_PTR is updated in the “PCIe Secondary Error Capabilities and Control Register” if R_MA Mask bit is clear in “PCIe Secondary Uncorrectable Error Mask Register”...
Page 89: Pci As Originating Interface
9. Error Handling > PCI as Originating Interface 4. Header is logged in the “PCIe Secondary Header Log 1 Register” and ERR_PTR is updated in the “PCIe Secondary Error Capabilities and Control Register” if R_TA Mask bit is clear in “PCIe Secondary Uncorrectable Error Mask Register”...
Page 90: Received Pci Errors
9. Error Handling > PCI as Originating Interface Table 16 describes the PEB383 behavior on a PCI Delayed transaction that is forwarded by a bridge to PCIe as a Memory Read request or an I/O Read/Write request, and the PCIe Interface returns a completion with Unsupported Request or Completer Abort Completion status for the request.
Page 91 9. Error Handling > PCI as Originating Interface 9.3.1.2 Uncorrectable Data Error on a Posted Write When the PEB383 receives posted write transaction that is addressed such that it crosses the bridge and the bridge detects an uncorrectable data error on its secondary PCI Interface, it does the following: 1.
Page 92 9. Error Handling > PCI as Originating Interface 9.3.1.4 Uncorrectable Address Error When the PEB383 detects an Uncorrectable Address Error, and parity error detection is enabled using the S_PERESP bit in “PCI Bridge Control and Interrupt Register”, the bridge takes the following actions: 1.
Page 93: Unsupported Request Completion Status
9. Error Handling > Timeout Errors 7. S_SERR bit is set in “PCI Control and Status Register” if an error message (Fatal/Non-Fatal) is generated and the SERR_EN bit is set in “PCI Control and Status Register” 8. FTL_ERR_DTD/NFTL_ERR_DTD bit is set in “PCIe Device Control and Status Register”...
Page 94: Pcie Completion Timeout Errors
9. Error Handling > Other Errors 9.4.1 PCIe Completion Timeout Errors The PCIe Completion Timeout function allows requestors to abort a non-posted request if the completion does not arrive within a reasonable period of time. When bridges act as initiators on PCIe on behalf of internally generated requests, and requests forwarded from a secondary interface in PCI mode, they act as endpoints for requests that they take ownership.
Page 95: Error Handling Tables
9. Error Handling > Error Handling Tables Error Handling Tables This section contains error handling information in a table format. Some of this information may overlap with error information discussed in previous sections of this chapter. Table 17: ECRC Errors Error Details Primary Reporting Mechanism ECRC Error...
Page 96: Table 19: Malformed Tlp Errors
9. Error Handling > Error Handling Tables Table 19: Malformed TLP Errors Error Details Primary Reporting Mechanism Payload exceeds max_payload_size “PCIe Uncorrectable Error Status Register” [MAL_TLP] 2. Optional ERR_FATAL or ERR_NONFATAL message sent. Write TLP payload does not match length specified in “PCIe Device Control and Status Register”...
Page 97: Table 20: Link And Flow Control Errors
9. Error Handling > Error Handling Tables Table 20: Link and Flow Control Errors Error Details Primary Reporting Mechanisms Receiver Overflow on header or data “PCIe Uncorrectable Error Status Register” [RXO]. “PCIe Device Control and Status Register” [FTL_ERR_DTD]/[NFTL_ERR_DTD]. 3. Optional ERR_FATAL or ERR_NONFATAL message sent. “PCI Control and Status Register”...
Page 98: Table 21: Uncorrectable Data/Address Errors
9. Error Handling > Error Handling Tables Table 21: Uncorrectable Data/Address Errors Error Details Primary Reporting Mechanism Secondary Reporting Mechanism PCIe as Originating Interface Uncorrectable Data Error on “PCI Control and Status Register” [D_PE]. “PCI Secondary Status and I/O Limit and the destination interface (PCI) Base Register”...
Page 99: Table 22: Received Master/Target Abort Error
9. Error Handling > Error Handling Tables Table 21: Uncorrectable Data/Address Errors (Continued) Error Details Primary Reporting Mechanism Secondary Reporting Mechanism Uncorrectable data error on “PCIe Device Control and Status Register” “PCIe Secondary Uncorrectable Error PCI delayed read completions. [FTL_ERR_DTD]/[NFTL_ERR_DTD]. Status Register”...
Page 100: Table 24: Request Errors
9. Error Handling > Error Handling Tables Table 23: Completion Errors Error Details Primary Reporting Mechanism Secondary Reporting Mechanism Completion received with “PCI Control and Status Register” [R_MA]. “PCI Secondary Status and I/O Limit and Unsupported Request in Base Register” [S_TA] is set if [MA_ERR] bit response to a request “PCI Bridge Control and Interrupt Register”...
Page 101: Reset And Clocking
Reset and Clocking Topics discussed include the following: • “Reset” • “Clocking” 10.1 Reset The PEB383 inputs resets from upstream devices, and drives reset to downstream devices. PCIE_PERSTn is the reset input to the bridge, and is normally connected to a power-on reset controller at the system level.
Page 102: Pcie Link Reset
10. Reset and Clocking > Reset 10.1.1 PCIe Link Reset PCIe resets flow from upstream devices. The PCIe Interface is a slave to resets through a system-level power-on reset controller connected to PCIE_PERSTn, or through inband messages from the root complex.
Page 103: Pci Bus Reset
10. Reset and Clocking > Reset 10.1.1.3 Hot Reset – Level 1 A hot reset is triggered by an in-band message from the root complex over the PCIe link. After application of hot reset, all registers are in their power-on reset state, except sticky bits which maintain their pre-reset values in order to aid in system diagnostics.
Page 104: Clocking
10. Reset and Clocking > Clocking 10.2 Clocking This section discusses clocking information for the PEB383’s PCIe and PCI Interfaces. 10.2.1 PCIe Clocking The PCIe clocking is shown in Figure 26. The 100-MHz reference clock, PCIE_REFCLK_n/p, drives a x(5/4) PLL to create a 125-MHz clock. The 125-MHz clock is further multiplied to create the Tx parallel to serial conversion, and clocking out the Tx pins, PCIE_TXD_n/p (The receive data is clocked into the PEB383 with the recovered clock.
Page 105: Pci Clocking
10. Reset and Clocking > Clocking 10.2.2 PCI Clocking The PCI clocking for the PEB383 is shown in Figure 27. The PEB383 supports clock master and slave mode, and is configured by the PCB design. The bridge drives up to four external clocks, PCI_CLKO[3:0], which are individually enabled through the “Clock Out Enable Function and Debug Register”.
Page 106 10. Reset and Clocking > Clocking a. This setting is based on the value of CS_MODE in the “PCI Miscellaneous Clock Straps Register”. PCI_CLKO[3:0] are connected to PCI devices, while PCI_CLKO[4] is connected to the PCI_CLK signal. The track length of the clock nets should be matched in length. 10.2.2.2 Slave Mode Clocking In slave clocking, PCI_CLKO[0] is disabled through the...
Page 107: Power Management
11. Power Management > Overview Power Management Topics discussed include the following: • “Overview” • “Power Management Capabilities” • “Power States” 11.1 Overview The PEB383 provides basic power management support to its PCI bus and PCIe link. PCI power management states are mapped to specific PCIe link states. The bridge also supports Active State Power Management (ASPM), where the device enters into power saving state and initiates exit when needed.
Page 108: Unsupported Features
11. Power Management > Power Management Capabilities 11.1.2 Unsupported Features • PCI power states: D1 and D2 • PCIe link states: L2 • PCI bus states • WAKE# to beacon • PME in D3 cold • Auxiliary power 11.2 Power Management Capabilities The PEB383 supports software driven D-state power management: D0, D3Hot, and D3Cold.
Page 109: L0 State
11. Power Management > Power States 11.3.2 L0 State This is the normal operational mode. 11.3.3 L0s State A low resume latency, energy-saving standby state. L0s support is required for ASPM. It is not applicable to PCI-PM compatible power management. 11.3.4 L1 State L1 is a high latency and low-power standby state.
Page 110: Link State Summary
11. Power Management > Power States 11.3.8 Link State Summary The link states are summarized in Table Table 28: PCIe Link States Software 100-MHz L state Description directed PM ASPM Reference Power internal PLL Fully active link Yes (D0) Yes (D0) Standby state Yes (D0) Low-power...
Page 111: Device Power States
11. Power Management > Power States 11.3.9 Device Power States The PEB383 supports the PCIe PCI-PM D0, D3Hot, and D3Cold (no Auxiliary power) device power management states. The bridge does not support the D1 and D2 power management states. 11.3.10 D0 State D0 is divided into two distinct sub states: the uninitialized sub-state and the active sub-state.
Page 112: D State Transitions
11. Power Management > Power States 11.3.13 D State Transitions The device power state transitions are shown in Figure 29. Software is responsible for controlling the state diagram through PWR_ST in the “PCI Power Management Control and Status Register” Figure 29: D State Transitions Power on Reset Uninitialized Power applied...
Page 113: Power State Summary
11. Power Management > Power States 11.3.15 Power State Summary The state summary is shown in Table Table 29: Power Management State Summary PEB383 Link Upstream State State State PCI Bus Description Operational Fully operational Operational PCIe link in standby Operational PCIe Link in L1 PME only...
Page 114: Power Saving Modes
11. Power Management > Power Saving Modes 11.4 Power Saving Modes The PEB383 provides several low power modes of operation, as described in Table Table 30: Power saving modes Input Conditions power saving activities PCI_CLK[3:0] internal Mode state ASPM gate enable traffic PCI_CLK[3:0] link state...
Page 115: Serial Eeprom
Serial EEPROM Topics discussed include the following: • “Overview” • “System Diagram” • “EEPROM Image” • “Functional Timing” 12.1 Overview The PEB383 uses an internal serial EEPROM Controller to configure its configuration space register (CSR) block with the values stored in an external serial EEPROM. The Controller is compatible with EEPROM devices that use the Serial Peripheral Interface, such as the Atmel AT25010A, AT25020A, AT25040A, AT25080A, AT25160A, AT25320A, and AT25640A.
Page 116: System Diagram
12. Serial EEPROM > System Diagram 12.2 System Diagram Figure 30 shows the EEPROM Controller interfacing an external EEPROM to the PEB383 configuration space. Figure 30: EEPROM Interface PEB38x SR_CLK SR_CSn EEPROM EEPROM Configuration SR_DOUT Controller Device Space Register SR_DIN The PEB383 internal clock block generates an EEPROM clock of 7.8 MHz to supply to the external EEPROM.
Page 117 12. Serial EEPROM > System Diagram If the identification code obtained through the first read is a correct value, then the EEPROM Controller determines that the EEPROM supports 9-bit addressing. The Controller then initiates one more read transaction to read the third and fourth locations of the EEPROM, where the value of the total number of bytes to be read (byte count) is located.
Page 118: Eeprom Image
12. Serial EEPROM > EEPROM Image 12.3 EEPROM Image The data structure to be maintained in the external EEPROM for successful operation of the EEPROM Controller is shown in Table 31. Note that the m and n in the Description column indicate the register number: they can point to any register in the entire CSR space.
Page 119: Functional Timing
12. Serial EEPROM > Functional Timing Table 31: EEPROM Image (Continued) Serial EEPROM Location Description Value FFFEh CSR register r Data [23:16] Any number FFFFh CSR register r Data [31:24] Any number 12.4 Functional Timing The EEPROM Controller outputs the data on the SR_DIN signal on every negative edge of the SR_CLK clock.
Page 120: Figure 32: 16-Bit Eeprom Read Timing
12. Serial EEPROM > Functional Timing Figure 32: 16-bit EEPROM Read Timing SR_CSn SR_CSn SR_CLK SR_CLK SR_DIN SR_DIN SR_DOUT SR_DOUT High - Z High - Z Opcode Opcode Address Address Data Data Figure 33: 9-bit EEPROM Write Timing SR_CSn SR_CSn SR_CLK SR_CLK SR_DIN...
Page 121: Figure 34: 16-Bit Eeprom Write Timing
12. Serial EEPROM > Functional Timing Figure 34: 16-bit EEPROM Write Timing SR_CSn SR_CSn SR_CLK SR_CLK SR_DIN SR_DIN SR_DOUT SR_DOUT SR_DOUT High-Z High-Z High-Z Opcode Opcode Address Address Data Data Figure 35: EEPROM WREN Instruction Timing SR_CSn SR_CSn SR_CLK SR_CLK SR_DIN SR_DIN High-Z...
Page 122 12. Serial EEPROM > Functional Timing PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 123: Jtag
JTAG Topics discussed include the following: • “Overview” • “TAP Controller Initialization” • “Instruction Register” • “Bypass Register” • “JTAG Device ID Register” • “JTAG Register Access” • “Dedicated Test Pins” • “Accessing SerDes TAP Controller” 13.1 Overview The JTAG Interface is compliant with IEEE 1149.6 Boundary Scan Testing of Advanced Digital Networks, as well as IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture standards.
Page 124: Tap Controller Initialization
13. JTAG > TAP Controller Initialization — Bypass — IDCODE — Clamp — User data select 13.2 TAP Controller Initialization After power-up of the PEB383, the TAP controller must be put into its test-logic-reset state to disable the JTAG logic and allow the bridge to function normally. This can be completed by driving the JTAG_TMS signal high and pulsing the JTAG_TCK signal five or more times, or by asserting the JTAG_TRSTn signal.
Page 125: Jtag Register Access
13. JTAG > JTAG Register Access 13.6 JTAG Register Access The JTAG Interface can be used for debug purposes in order to perform read and write access of the PEB383’s configuration registers. It also can perform read accesses on the performance registers without impacting active transactions.
Page 126: Read Access To Registers From Jtag Interface
13. JTAG > JTAG Register Access • DR[16:0] = 17b’0 Note: Bit 0 is shifted first, and bit 66 is shifted last. 3. Move to the “Run-test idle” state and loop in this state for a minimum of 20 TCK cycles. 4.
Page 127: Dedicated Test Pins
13. JTAG > Dedicated Test Pins • Verify that the Ready bit is at logic high and the Error bit is at logic low. Note: To prevent corruption, the DR register must be loaded as described in step 2 while shifting out through JTAG_TDO for observation.
Page 128 13. JTAG > Accessing SerDes TAP Controller PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 129: Register Descriptions
Register Descriptions Topics discussed include the following: • “Overview” • “PCI Configuration Space” • “Register Map” • “Upstream Non-transparent Address Remapping Registers” • “PCI Capability Registers” • “PCIe Capability Registers” • “Downstream Non-transparent Address Remapping Registers” • “Advanced Error Reporting Capability Registers” •...
Page 130 14. Register Descriptions > Overview • ReservedP - The value in this field must be preserved during a write access. • Undefined - This value is undefined after reset because it is based on a bit setting, a pin setting, or a power-up setting.
Page 131: Pci Configuration Space
14. Register Descriptions > PCI Configuration Space 14.2 PCI Configuration Space The PEB383 device uses a standard PCI Type 1 configuration header. Table 32 shows the PCI 3.0 compatible Type 1 configuration space with constant values shown populated in the appropriate header fields.
Page 132: Table 34: Power Management Capability Registers
14. Register Descriptions > PCI Configuration Space The power management capability registers are shown below. Table 34: Power Management Capability Registers Offset Page Power Management Capabilities Next Pointer Capability ID 0x0A0 Data bridge support PMCSR 0x0A4 extensions (Reserved 0x00) (Reserved 0x00) The PCIe capability registers are shown below.
Page 133 14. Register Descriptions > PCI Configuration Space Table 36: Advanced Error Reporting Capability Registers (Continued) Offset Page 0x11C 0x120 Header Log Register 0x124 0x128 Secondary Uncorrectable Error Status Register 0x12C Secondary Uncorrectable Error Mask Register 0x130 Secondary Uncorrectable Error Severity Register 0x134 Secondary Error Capabilities and Control Register 0x138...
Page 134: Register Map
14. Register Descriptions > Register Map 14.3 Register Map The following table lists the register map for the PEB383. Table 37: Register Map Offset Name 0x000 PCI_ID “PCI Identification Register” 0x004 PCI_CSR “PCI Control and Status Register” 0x008 PCI_CLASS “PCI Class Register” 0x00C PCI_MISC0 “PCI Miscellaneous 0 Register”...
Page 135 14. Register Descriptions > Register Map Table 37: Register Map (Continued) Offset Name 0x068 NTMA_CTRL “NTMA Control Register” 0x06C NTMA_PRI_BASEUPPER “NTMA Primary Upper Base Register” 0x070 NTMA_SEC_LBASE “NTMA Secondary Lower Base Register” 0x074 NTMA_SEC_BASEUPPER “NTMA Secondary Upper Base Register” 0x078 NTMA_SEC_LIMIT “NTMA Secondary Lower Limit Register”...
Page 136 14. Register Descriptions > Register Map Table 37: Register Map (Continued) Offset Name 0x108 PCIE_UERR_MASK “PCIe Uncorrectable Error Mask Register” 0x10C PCIE_UERR_SEV “PCIe Uncorrectable Error Severity Register” 0x110 PCIE_COR_ERR “PCIe Correctable Error Status Register” 0x114 PCIE_COR_MASK “PCIe Correctable Error Mask Register” 0x118 PCIE_AERR_CAP_CTRL “PCIe Advanced Error Capabilities and Control Register”...
Page 137: Pci Identification Register
Vendor ID 0x10E3 This field indicates the silicon vendor identification number. By default, the PEB383 device reports a value of 0x10E3 indicating the vendor as IDT (formerly Tundra). Integrated Device Technology, Inc. PEB383 User Manual Confidential - NDA Required July 25, 2011...
Page 138: Pci Control And Status Register
14. Register Descriptions > Register Map 14.3.2 PCI Control and Status Register This register defines configurable parameters for how devices interact with the PCI bus, and indicates status information for PCI bus events. Register name: PCI_CSR Register offset: 0x004 Reset value: 0x_0010_0000 Bits 31:24 D_PE...
Page 139 14. Register Descriptions > Register Map (Continued) Bits Name Description Type Reset value R_TA Received Target-Abort R/W1C This bit is set when the bridge receives a Completion with Completer Abort Completion Status on its PCIe Interface. 0 = Completer Abort Completion Status not received on the PCIe Interface 1 = Completer Abort Completion Status received on the PCIe Interface...
Page 140 14. Register Descriptions > Register Map (Continued) Bits Name Description Type Reset value INT_DIS Interrupt Disable The PEB383 does not generate internal interrupts. MFBBC Fast Back-to-Back Enable This field does not apply for PCIe bridges. It always reads 0. SERR_EN SERR# Enable This bit enables reporting of non-fatal and fatal errors to the Root Complex.
Page 141 14. Register Descriptions > Register Map (Continued) Bits Name Description Type Reset value Memory Space Enable This bit controls the PEB383’s response as a target to memory accesses on the PCIe Interface that address a device that resides behind the bridge in both the non-prefetchable and prefetchable memory ranges, or targets a memory-mapped location within the bridge itself.
Page 142: Pci Class Register
14. Register Descriptions > Register Map 14.3.3 PCI Class Register This register indicates the PCI classification of the PEB383. Register name: PCI_CLASS Register offset: 0x008 Reset value: 0x0604_0001 Bits 31:24 BASE 23:16 15:08 PROG 07:00 Bits Name Description Type Reset value 31:24 BASE Base Class...
Page 143: Pci Miscellaneous 0 Register
14. Register Descriptions > Register Map 14.3.4 PCI Miscellaneous 0 Register This register controls miscellaneous PCI functions, such as the latency timer value and cacheline size. Register name: PCI_MISC0 Register offset: 0x00C Reset value: 0x0001_0000 Bits 31:24 BISTC SBIST Reserved CCODE 23:16 H_TYPE...
Page 144: Pci Bus Number Register
14. Register Descriptions > Register Map 14.3.5 PCI Bus Number Register Register name: PCI_BUSNUM Register offset: 0x018 Reset value: Undefined Bits 31:24 S_LTIMER S_LTIMER_8 23:16 SUB_BUS_NUM 15:08 S_BUS_NUM 07:00 P_BUS_NUM Bits Name Description Type Reset value 31:27 S_LTIMER Secondary Latency Timer Undefined This value is used by the PEB383 to perform burst transfers on the PCI Interface.
Page 145: Pci Secondary Status And I/O Limit And Base Register
14. Register Descriptions > Register Map 14.3.6 PCI Secondary Status and I/O Limit and Base Register Register name: PCI_MISC1_P Register offset: 0x01C Reset value: 0x02A0_0101 Bits 31:24 D_PE S_SERR R_MA R_TA S_TA DEVSEL MDP_D 23:16 TFBBC Reserved DEV66 Reserved 15:08 IO_LA ADD_CAP1 07:00...
Page 146 14. Register Descriptions > Register Map (Continued) Bits Name Description Type Reset value S_TA Signaled Target Abort R/W1C The PEB383 sets this bit to report the signaling of Target-Abort as target of a transaction on the PCI Interface. 0 = No Target-Abort signaled. 1 = Target-Abort signaled by the PEB383 on its PCI Interface.
Page 147 14. Register Descriptions > Register Map (Continued) Bits Name Description Type Reset value 03:00 ADD_CAP2 Addressing Capability The PEB383 supports 32-bit I/O addressing. Integrated Device Technology, Inc. PEB383 User Manual Confidential - NDA Required July 25, 2011...
Page 148: Pci Memory Base And Limit Register
14. Register Descriptions > Register Map 14.3.7 PCI Memory Base and Limit Register Register name: PCI_MIO_BL Register offset: 0x020 Reset value: 0x0000_0000 Bits 31:24 23:16 Reserved 15:08 07:00 Reserved Bits Name Description Type Reset value 31:20 Memory Limit Address This field is used in conjunction with the Memory Base Address for forwarding memory-mapped I/O transactions.
Page 149: Pci Pfm Base And Limit Register
14. Register Descriptions > Register Map 14.3.8 PCI PFM Base and Limit Register Register name: PCI_PFM_BL Register offset: 0x024 Reset value: 0x0001_0001 Bits 31:24 23:16 ADD_LA_64 15:08 07:00 ADD_BA_64 Bits Name Description Type Reset value 31:20 Prefetchable Memory Limit Address This field is used in conjunction with Memory Base Address for forwarding memory-mapped I/O transactions.
Page 150: Pci Pfm Base Upper 32 Address Register
14. Register Descriptions > Register Map 14.3.9 PCI PFM Base Upper 32 Address Register Register name: PCI_PFM_B_UPPER Register offset: 0x028 Reset value: 0x0000_0000 Bits 31:24 23:16 15:08 07:00 Bits Name Description Type Reset value 31:00 Prefetchable Memory Base Upper 32-bit Address This field is used in conjunction with BA in the “PCI PFM Base and Limit Register”...
Page 151: Pci I/O Address Upper 16 Register
14. Register Descriptions > Register Map 14.3.11 PCI I/O Address Upper 16 Register Register name: PCI_IO_UPPER Register offset: 0x030 Reset value: 0x0000_0000 Bits 31:24 IO_LA 23:16 IO_LA 15:08 IO_BA 07:00 IO_BA Bits Name Description Type Reset value 31:16 IO_LA I/O Limit Address Upper 16-bits 0x0000 This field is used in conjunction with IO_LA in the “PCI...
Page 152: Pci Capability Pointer Register
14. Register Descriptions > Register Map 14.3.12 PCI Capability Pointer Register Register name: PCI_CAP Register offset: 0x034 Reset value: 0x0000_00A0 Bits 31:24 Reserved 23:16 Reserved 15:08 Reserved 07:00 CAP_PTR Bits Name Description Type Reset value 31:08 Reserved Reserved 07:00 CAP_PTR Capabilities Pointer 0x0A0 By default the next capability pointer is 0xA0...
Page 153: Pci Bridge Control And Interrupt Register
14. Register Descriptions > Register Map 14.3.13 PCI Bridge Control and Interrupt Register Register name: PCI_MISC2 Register offset: 0x03C Reset value: 0x0000_00FF Bits 31:24 Reserved DISCARD DISCARD_ DISCARD2 DISCARD1 _SERR STAT 23:16 S_FPTP_ S_RESET MA_ERR VGA_ VGA_EN ISA_EN SERR_EN 16BIT_EN PERESP 15:08 INT_PIN...
Page 154 14. Register Descriptions > Register Map (Continued) Bits Name Description Type Reset value DISCARD2 Secondary Discard Timer This bit determines the number of PCI clocks that the bridge waits for a master on the PCI Interface to repeat a Delayed Transaction request.
Page 155 14. Register Descriptions > Register Map (Continued) Bits Name Description Type Reset value MA_ERR Master-Abort Mode This bit controls the behavior of a bridge when it receives a Master-Abort termination (for example, an Unsupported Request on PCIe) on either interface. 0 = Do not report Master-Aborts.
Page 156 14. Register Descriptions > Register Map (Continued) Bits Name Description Type Reset value VGA_EN VGA Enable This bit modifies the response of the bridge to VGA-compatible addresses. If this bit is set, the bridge forwards the following accesses on the PCIe Interface to the PCI Interface (and, conversely, block the forwarding of these addresses from the secondary interface to the PCIe Interface):...
Page 157 14. Register Descriptions > Register Map (Continued) Bits Name Description Type Reset value ISA_EN ISA Enable This bit modifies the response by the PEB383 to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and Limit registers and are in the first 64 KB of PCI I/O address space (0000 0000h to 0000 FFFFh).
Page 158 14. Register Descriptions > Register Map (Continued) Bits Name Description Type Reset value S_PERESP Parity Error Response Enable This bit controls the PEB383’s response to uncorrectable address, attribute, and data errors on the PCI Interface. If this bit is set, the bridge must take its normal action when one of these errors is detected.
Page 159: Secondary Retry Count Register
14. Register Descriptions > Register Map 14.3.14 Secondary Retry Count Register Register name: SEC_RETRY_CNT Register offset: 0x040 Reset value: 0x0000_AA00 Bits 31:24 Reserved 23:16 Reserved Reserved PARK 15:8 DTL3 DTL2 DTL1 DTL0 Reserved SEC_RT_CNT Bits Name Description Type Reset value 31:25 Reserved Reserved...
Page 160 14. Register Descriptions > Register Map (Continued) Bits Name Description Type Reset value 11:10 DTL0 Delayed Transaction Limit for PCI Device 1: 0b10 0b01; max one delayed transaction for device 1 0b10; max two delayed transaction for device 1 0b11; max three delayed transaction for device 1 0b00;...
Page 161: Pci Miscellaneous Control And Status Register
14. Register Descriptions > Register Map 14.3.15 PCI Miscellaneous Control and Status Register Register name: PCI_MISC_CSR Register offset: 0x044 Reset value: 0x7D10_1900 Bits 31:24 Reserved EN_ARB EN_ARB3 EN_ARB2 EN_ARB1 EN_ARB0 Reserved P_ERR 23:16 STC_EN Reserved ARB_PRI ARB_PRI3 ARB_PRI2 ARB_PRI1 ARB_PRI0 15:08 Reserved CPL_INIT_COUNT...
Page 162 14. Register Descriptions > Register Map (Continued) Bits Name Description Type Reset value STC_EN Short-term Caching Enable 0 = Disable short-term caching 1 = Enable short-term caching 22:21 Reserved Reserved ARB_PRI Internal Arbiter Priority This bit sets priority for PEB383 requests. 0 = Internal requests from the PEB383 are assigned low priority 1 = Internal requests from the PEB383 are assigned high...
Page 163 14. Register Descriptions > Register Map (Continued) Bits Name Description Type Reset value 10:08 CFG_RT Configuration Retry Timer The PEB383 returns the Completion with CRS completion status for the received Type 1 configuration requests if this timer is expired before receiving the Completion from the targeted secondary device.
Page 164: Pci Miscellaneous Clock Straps Register
14. Register Descriptions > Register Map 14.3.16 PCI Miscellaneous Clock Straps Register Register name: PCI_MISC_CLK_STRAPS Register offset: 0x048 Reset value: 0x0000_0100 Bits 31:24 Reserved 23:16 Reserved 15:08 Reserved CSR_SEL_ 07:00 LEGACY Reserved PCGE OP_MODE CS_MODE Bits Name Description Type Reset value 31:9 Reserved Reserved...
Page 165 14. Register Descriptions > Register Map (Continued) Bits Name Description Type Reset value CS_MODE Clock Speed Mode This field defines the clock speed when OP_MODE is set to 1 according to the following code points: 0bX00 = 25-MHz PCI mode 0bX01 = 33-MHz PCI mode 0bX10 = 50-MHz PCI mode 0bX11 = 66-MHz PCI mode...
Page 166: Upstream Posted Write Threshold Register
14. Register Descriptions > Register Map 14.3.17 Upstream Posted Write Threshold Register Register name: UPST_PWR_THRES Register offset: 0x04C Reset value: 0x0000_0307 Bits 31:24 Reserved 23:16 Reserved 15:8 Reserved MAX_BUF_ALOC Reserved UPST_PWR_THRES Bits Name Description Type Reset value 31:10 Reserved Reserved. MAX_BUF_ALOC Maximum Buffer Allocation This field determines the maximum completion buffer...
Page 167: Completion Timeout Register
14. Register Descriptions > Register Map 14.3.18 Completion Timeout Register Register name: CPL_TIMEOUT Register offset: 0x050 Reset value: 0x8009_8968 Bits 31:24 CPL_TO_ CPL_TO_VALUE 23:16 CPL_TO_VALUE 15:08 CPL_TO_VALUE 07:00 CPL_TO_VALUE Bits Name Description Type Reset value CPL_TO_EN Completion Timeout Enable This bit enables/disables the Completion Timeout function. The PEB383 handles an upstream non-posted request as if completion is returned with UR if the completion is not returned before its Completion Timeout Timer is expired.
Page 168: Clock Out Enable Function And Debug Register
14. Register Descriptions > Register Map 14.3.19 Clock Out Enable Function and Debug Register Register name: CLKOUT_ENB_FUNC_DBG Register offset: 0x054 Reset value: 0x0000_1F00 Bits 31:24 Reserved 23:16 Reserved 15:08 Reserved CLKOUT_ENB 07:00 Reserved FUNC_DBG Bits Name Description Type Reset value 31:13 Reserved Reserved.
Page 169: Serrdis_Opqen_Dtc Register
14. Register Descriptions > Register Map 14.3.20 SERRDIS_OPQEN_DTC Register Register name: SERRDIS_OPQEN_DTC Register offset: 0x058 Reset value: 0x0000_0100 Bits 31:24 Reserved 23:16 Reserved 15:08 Reserved ST_DIST_ Reserved SEC_DIST 07:00 Reserved Bits Name Description Type Reset value 31:11 Reserved Reserved ST_DIST_EN Short Term Discard Timer Enable 0 = Secondary discard timer value sets to either 0x03FF (1K PCI clock cycles) or 0x7FFF (32 K PCI clock cycles)
Page 170: Upstream Non-Transparent Address Remapping Registers
14. Register Descriptions > Upstream Non-transparent Address Remapping Registers 14.4 Upstream Non-transparent Address Remapping Registers The PEB383 supports address remapping, which is one of the requirements of non-transparent bridging. All transactions that fall in the non-transparent address range are mapped to different address locations according to following device-specific registers.
Page 171: Ntma Primary Upper Base Register
14. Register Descriptions > Upstream Non-transparent Address Remapping Registers 14.4.2 NTMA Primary Upper Base Register Register name: NTMA_PRI_BASEUPPER Register offset: 0x06C Reset value: 0x0000_0000 Bits 31:24 NTMA_UBA 23:16 NTMA_UBA 15:08 NTMA_UBA 07:00 NTMA_UBA Bits Name Description Type Reset value 31:00 NTMA_UBA NTMA Primary upper base address.
Page 172: Ntma Secondary Upper Base Register
14. Register Descriptions > Upstream Non-transparent Address Remapping Registers 14.4.4 NTMA Secondary Upper Base Register Register name: NTMA_SEC_BASEUPPER Register offset: 0x074 Reset value: 0x0000_0000 Bits 31:24 NTMA_UBA 23:16 NTMA_UBA 15:08 NTMA_UBA 07:00 NTMA_UBA Bits Name Description Type Reset value 31:00 NTMA_UBA NTMA Secondary upper base address.
Page 173: Ntma Secondary Upper Limit Register
14. Register Descriptions > PCI Capability Registers 14.4.6 NTMA Secondary Upper Limit Register Register name: NTMA_SEC_UPPER_LIMIT Register offset: 0x07C Reset value: 0x0000_0000 Bits 31:24 NTMA_ULA 23:16 NTMA_ULA 15:08 NTMA_ULA 07:00 NTMA_ULA Bits Name Description Type Reset value 31:00 NTMA_ULA NTMA Secondary Upper limit address. 14.5 PCI Capability Registers The PEB383 device supports PCI and PCIe extended capabilities options.
Page 174: Ssid Capability Register
14. Register Descriptions > PCI Capability Registers 14.5.2 SSID Capability Register Register name: SSID_CAP Register offset: 0x060 Reset value: 0x0000_A00D Bits 31:24 Reserved 23:16 Reserved 15:08 CAP_PTR 07:00 CAP_ID Bits Name Description Type Reset value 31:16 Reserved Reserved 15:08 CAP_PTR Capabilities Pointer 0xA0 This register contains the head pointer for the capability list...
Page 175: Ssid Id Register
14. Register Descriptions > PCI Capability Registers 14.5.3 SSID ID Register The values in this register can be written by EEPROM. Register name: SSID_ID Register offset: 0x064 Reset value: 0x0000_0000 Bits 31:24 SSID 23:16 SSID 15:08 SSVID 07:00 SSVID Bits Name Description Type...
Page 176: Pci Power Management Capability Register
14. Register Descriptions > PCI Capability Registers 14.5.4 PCI Power Management Capability Register This register defines bytes 0 to 3 of the power management capability option. Register name: PCI_PMC Register offset: 0x0A0 Reset value: 0x7803_C001 Bits 31:24 PME_SUP D2_SP D1_SP AUX_CUR 23:16 AUX_CUR...
Page 177 14. Register Descriptions > PCI Capability Registers (Continued) Bits Name Description Type Reset value 18:16 PM_VER Version This field indicates a version number of 011 indicating it supports the PCI Bus Power Management Interface Specification (Revision 1.2). 15:8 NXT_PTR Next Pointer 0xC0 This field points to the next capability option: “PCIe...
Page 178: Pci Power Management Control And Status Register
14. Register Descriptions > PCI Capability Registers 14.5.5 PCI Power Management Control and Status Register This register defines the control and status registers of the power management capability option. Register name: PCI_PMCS Register offset: 0x0A4 Reset value: 0x0000_0008 Bits 31:24 DATA 23:16 BPCCE...
Page 179 14. Register Descriptions > PCI Capability Registers (Continued) Bits Name Description Type Reset value PME_ST Power PME Status This field indicates whether this device can generate PME#. This field’s value is independent of whether the Power PME Enable field is set to 1. 0 = No PME# is being asserted by this PCI function.
Page 180: Eeprom Control Register
14. Register Descriptions > PCI Capability Registers 14.5.6 EEPROM Control Register Register name: EE_CTRL Register offset: 0x0AC Reset value: Undefined Bits 31:24 Reserved ADD_WIDTH BUSY CMD_VLD 23:16 15:08 07:00 DATA Bits Name Description Type Reset value 31:30 Reserved Reserved 29:28 Command 01 = Read 10 = Write...
Page 181: Secondary Bus Device Mask Register
14. Register Descriptions > PCI Capability Registers 14.5.7 Secondary Bus Device Mask Register This register provides a method to support private devices on the PCI bus. The process of converting Type 1 configuration transactions to Type 0 configuration transactions is modified by the contents of this register.
Page 182 14. Register Descriptions > PCI Capability Registers (Continued) Bits Name Description Type Reset Value DEVMSK_6 Device Mask 6 0 = Rerouting disabled for device 6. 1 = Block assertion of PCI_AD (Pin 22) for configuration transactions to device 6, assert pin PCI_AD (Pin 31) instead.
Page 183: Short-Term Caching Period Register
14. Register Descriptions > PCI Capability Registers 14.5.8 Short-term Caching Period Register Register name: STERM_CACHING_PERIOD Register offset: 0x0B4 Reset value: 0x0000_0040 Bits 31:24 ST_CACHE 23:16 ST_CACHE 15:08 ST_CACHE 07:00 ST_CACHE Bits Name Description Type Reset value 31:00 ST_CACHE Short Term caching period 0x0000_ 0040 This field indicates the number of PCI clock cycles allowed...
Page 184: Retry Timer Status Register
14. Register Descriptions > PCI Capability Registers 14.5.9 Retry Timer Status Register Register name: TIMER_STATUS Register offset: 0x0B8 Reset value: 0x0000_0000 Bits 31:24 Reserved 23:16 Reserved 15:08 Reserved 07:00 Reserved SEC_DIS_ Reserved SEC_R_ STAT STAT Bits Name Description Type Reset value 31:03 Reserved Reserved...
Page 185: Prefetch Control Register
14. Register Descriptions > PCI Capability Registers 14.5.10 Prefetch Control Register Register name: PREF_CTRL Register offset: 0x0BC Reset value: 0x0300_0041 Bits 31:24 Reserved P_MR P_MRL P_MRM 23:16 MRL_66 MRL_33 15:08 MRL_33 MRM_66 07:00 MRM_66 MRM_33 Bits Name Description Type Reset value 31:27 Reserved Reserved...
Page 186 14. Register Descriptions > PCI Capability Registers (Continued) Bits Name Description Type Reset value 11:6 MRM_66 This bit indicates the threshold parameter for Memory read 0x01 multiple command in 66-MHz PCI mode. Unit is 64-byte chunk. 6’h00 = 64 bytes 6’h01 = 128 bytes 6’h3F = 4096 bytes MRM_33...
Page 187: Pcie Capability Registers
14. Register Descriptions > PCIe Capability Registers 14.6 PCIe Capability Registers In the PEB383, the PCIe capability is located in PCI 2.3 configuration space at 0x0C0 and contains 20 bytes. When the PEB383 operates in “Legacy Mode” the following registers are not supported and are treated as reserved: •...
Page 188 14. Register Descriptions > PCIe Capability Registers (Continued) Bits Name Description Type Reset value 07:00 CAP_ID Capability ID 0x10 This field contains the value 0x10 indicating a PCIe capability option. PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 189: Pcie Device Capabilities Register
14. Register Descriptions > PCIe Capability Registers 14.6.2 PCIe Device Capabilities Register This register defines bytes 4 to 7 of the PCIe capability option. Register name: PCIE_DEV_CAP Register offset: 0x0C4 Reset value: 0x0000_8000 Bits 31:24 Reserved PL_SCL PL_VAL 23:16 PL_VAL Reserved 15:08 ROL_BAS_...
Page 190 14. Register Descriptions > PCIe Capability Registers (Continued) Bits Name Description Type Reset value 14:12 Reserved The Value read from these bits is 0b000. Previous version of the PCI specification had defined theses bits, they are now defined as read only, and return 0b000. System software is permitted to write any value to these bits.
Page 191: Pcie Device Control And Status Register
14. Register Descriptions > PCIe Capability Registers 14.6.3 PCIe Device Control and Status Register This register defines bytes 8 to 11 of the PCIe capability option. Register name: PCIE_DEV_CSR Register offset: 0x0C8 Reset value: 0x0000_2000 Bits 31:24 Reserved 23:16 Reserved TRAN_ AUX_PWR UNS_REQ_...
Page 192 14. Register Descriptions > PCIe Capability Registers (Continued) Bits Name Description Type Reset value NFTL_ERR_DTD PCIe Non-Fatal Error Detected R/W1C This field indicates whether a non-fatal error was detected. 0 = No error detected. 1 = Error detected. Writing 1 clears this error. COR_ERR_DTD PCIe Correctable Error Detected R/W1C...
Page 193 14. Register Descriptions > PCIe Capability Registers (Continued) Bits Name Description Type Reset value MAX_PAY_SIZE PCIe Maximum Payload Size This field indicates the maximum payload size that can be used for data transmission by the PEB383. This must be a subset of the size reported by MAX_SIZE in “PCIe Device Capabilities...
Page 194: Pcie Link Capabilities Register
14. Register Descriptions > PCIe Capability Registers 14.6.4 PCIe Link Capabilities Register Register name: PCIE_LNK_CAP Register offset: 0x0CC Reset value: 0x0001_3C11 Bits 31:24 PORT_NUM 23:16 Reserved DLL_LNK_ SRP_DWN CLK_PWR_ L1_EXIT ACT_REP_ _ERR_REP _CAP 15:08 L1_EXIT L0S_EXIT ASPM MAX_WIDTH 07:00 MAX_WIDTH MAX_SPEED Bits Name...
Page 195 14. Register Descriptions > PCIe Capability Registers (Continued) Bits Name Description Type Reset value CLK_PWR_MGT Clock Power Management 0 = The component does not have this capability, and the reference clock(s) must not be removed in these link states. 1 = The component tolerates the removal of any reference clock(s) via the “clock request”...
Page 196: Pcie Link Control Register
14. Register Descriptions > PCIe Capability Registers 14.6.5 PCIe Link Control Register This register defines bytes 16 to 17 of the PCIe capability option. Register name: PCIE_LNK_CSR Register offset: 0x0D0 Reset value: 0x0011_0000 Bits 31:24 Reserved DLL_LNK_ SLT_CLK_ Reserved NEG_LNK_WIDTH CONFIG 23:16 NEG_LNK_WIDTH...
Page 197 14. Register Descriptions > PCIe Capability Registers (Continued) Bits Name Description Type Reset value COM_CLK PCIe Common Clock Configuration This field selects between a distributed common reference clock or an asynchronous reference clock. After setting both ends of the link to the same value, the link must be retrained from the bridge side of the link.
Page 198: Downstream Non-Transparent Address Remapping Registers
14. Register Descriptions > Downstream Non-transparent Address Remapping Registers 14.7 Downstream Non-transparent Address Remapping Registers 14.7.1 Secondary Bus Non-prefetchable Address Remap Control Register Register name: AR_SBNPCTRL Register offset: 0x0E4 Reset value: 0x0000_0000 Bits 31:24 SEC_NP_LBASE 23:16 SEC_NP_LBASE Reserved 15:08 Reserved IO_SIZE 07:00 Reserved...
Page 199: Secondary Bus Non-Prefetchable Upper Base Address Remap Register
14. Register Descriptions > Downstream Non-transparent Address Remapping Registers 14.7.2 Secondary Bus Non-prefetchable Upper Base Address Remap Register Register name: AR_SBNPBASE Register offset: 0x0E8 Reset value: 0x0000_0000 Bits 31:24 SEC_NP_UBA 23:16 SEC_NP_UBA 15:08 SEC_NP_UBA 07:00 SEC_NP_UBA Bits Name Description Type Reset value 31:00 SEC_NP_UBA...
Page 200: Secondary Bus Prefetchable Upper Base Address Remap Register
14. Register Descriptions > Downstream Non-transparent Address Remapping Registers 14.7.4 Secondary Bus Prefetchable Upper Base Address Remap Register Register name: AR_SBPREBASEUPPER Register offset: 0x0F0 Reset value: 0x0000_0000 Bits 31:24 SEC_PRE_UBA 23:16 SEC_PRE_UBA 15:08 SEC_PRE_UBA 07:00 SEC_PRE_UBA Bits Name Description Type Reset value 31:00 SEC_PRE_UBA...
Page 201: Primary Bus Non-Prefetchable Upper Limit Remap Register
14. Register Descriptions > Downstream Non-transparent Address Remapping Registers 14.7.6 Primary Bus Non-prefetchable Upper Limit Remap Register Register name: AR_PBNPLIMITUPPER Register offset: 0x0F8 Reset value: 0x0000_0000 Bits 31:24 PRI_NP_ULA 23:16 PRI_NP_ULA 15:08 PRI_NP_ULA 07:00 PRI_NP_ULA Bits Name Description Type Reset value 31:00 PRI_NP_ULA Primary bus non-prefetchable upper Limit...
Page 202: Advanced Error Reporting Capability Registers
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8 Advanced Error Reporting Capability Registers When the PEB383 operates in “Legacy Mode” the following registers are not supported and are treated as reserved: • “PCIe Capability Registers” • “Advanced Error Reporting Capability Registers” 14.8.1 PCIe Advanced Error Reporting Capability Register Register name: PCIE_ADV_ERR_CAP...
Page 203: Pcie Uncorrectable Error Status Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.2 PCIe Uncorrectable Error Status Register Register name: PCIE_UNC_ERR_STAT Register offset: 0x104 Reset value: 0x0000_0000 Bits 31:24 Reserved 23:16 Reserved ECRC MAL_TLP 15:08 FCPE PTLP Reserved 07:00 Reserved DLPE Reserved Undefined Bits Name Description...
Page 204: Pcie Uncorrectable Error Mask Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.3 PCIe Uncorrectable Error Mask Register Register name: PCIE_UERR_MASK Register offset: 0x108 Reset value: 0x0000_0000 Bits 31:24 Reserved 23:16 Reserved ECRC MAL_TLP 15:08 FCPE PTLP Reserved 07:00 Reserved DLPE Reserved Undefined Bits Name Description...
Page 205: Pcie Uncorrectable Error Severity Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.4 PCIe Uncorrectable Error Severity Register Register name: PCIE_UNC_ERR_SEV Register offset: 0x10C Reset value: 0x0006_2030 Bits 31:24 Reserved 23:16 Reserved ECRC MAL_TLP 15:08 FCPE PTLP Reserved 07:00 Reserved SDES DLPE Reserved Unused Bits Name...
Page 206: Pcie Correctable Error Status Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.5 PCIe Correctable Error Status Register Register name: PCIE_COR_ERR Register offset: 0x110 Reset value: 0x0000_0000 Bits 31:24 Reserved 23:16 Reserved 15:08 Reserved ANFE RT_TO Reserved RN_RO 07:00 B_DLLP B_TLP Reserved Bits Name Description Type...
Page 207: Pcie Correctable Error Mask Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.6 PCIe Correctable Error Mask Register Register name: PCIE_COR_MASK Register offset: 0x114 Reset value: 0x0000_2000 Bits 31:24 Reserved 23:16 Reserved 15:08 Reserved ANFE RT_TO Reserved RN_RO 07:00 B_DLLP B_TLP Reserved Bits Name Description Type...
Page 208: Pcie Advanced Error Capabilities And Control Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.7 PCIe Advanced Error Capabilities and Control Register Register name: PCIE_ADV_ERR_CAP_CTRL Register offset: 0x118 Reset value: 0x0000_00A0 Bits 31:24 Reserved 23:16 Reserved 15:08 Reserved EC_EN 07:00 EC_CAP EG_EN EG_CAP ERR_PTR Bits Name Description Type...
Page 209: Pcie Header Log 1 Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.8 PCIe Header Log 1 Register Register name: PCIE_HL1 Register offset: 0x11C Reset value: 0x0000_0000 Bits 31:24 HEADER[127:120] 23:16 HEADER[119:112] 15:08 HEADER[111:104] 07:00 HEADER[103:96] Bits Name Description Type Reset value 31:00 HEADER[127:96] Header of TLP associated with error.
Page 210: Pcie Header Log 3 Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.10 PCIe Header Log 3 Register Register name: PCIE_HL3 Register offset: 0x124 Reset value: 0x0000_0000 Bits 31:24 HEADER[63:56] 23:16 HEADER[55:48] 15:08 HEADER[47:40] 07:00 HEADER[39:32] Bits Name Description Type Reset value 31:00 HEADER[63:32] Header of TLP associated with error.
Page 211: Pcie Secondary Uncorrectable Error Status Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.12 PCIe Secondary Uncorrectable Error Status Register Register name: PCIE_SEC_UERR_STAT Register offset: 0x12C Reset value: 0x0000_0000 Bits 31:24 Reserved 23:16 Reserved 15:08 Reserved IB_ERR SERR_AD PERR_AD DTDTE UADD_ UATT_ERR 07:00 UDERR USCM USCE Reserved...
Page 212: Pcie Secondary Uncorrectable Error Mask Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.13 PCIe Secondary Uncorrectable Error Mask Register Register name: PCIE_SEC_UERR_MASK Register offset: 0x130 Reset value: 0x0000_17A8 Bits 31:24 Reserved 23:16 Reserved 15:08 Reserved IB_ERR SERR_AD PERR_AD DTDTE UADD_ UATT_ERR 07:00 UDERR USCM USCE Reserved...
Page 213: Pcie Secondary Uncorrectable Error Severity Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.14 PCIe Secondary Uncorrectable Error Severity Register Register name: PCIE_SEC_UERR_SEV Register offset: 0x134 Reset value: 0x0000_1340 Bits 31:24 Reserved 23:16 Reserved 15:08 Reserved IB_ERR SERR_AD PERR_AD DTDTE UADD_ UATT_ERR 07:00 UDERR USCM USCE Reserved...
Page 214: Pcie Secondary Error Capabilities And Control Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.15 PCIe Secondary Error Capabilities and Control Register Register name: PCIE_ERR_CAP_CTRL Register offset: 0x138 Reset value: 0x0000_0000 Bits 31:24 Reserved 23:16 Reserved 15:08 Reserved 07:00 Reserved SUFEP Bits Name Description Type Reset value 31:05 Reserved...
Page 215: Pcie Secondary Header Log 2 Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.17 PCIe Secondary Header Log 2 Register Register name: PCIE_SEC_HL2 Register offset: 0x140 Reset value: 0x0000_0000 Bits 31:24 Reserved 23:16 Reserved 15:08 Reserved TRAN_CU 07:00 TRAN_CL TRAN_ATT[35:32] Bits Name Description Type Reset value 31:12 Reserved...
Page 216: Pcie Secondary Header Log 3 Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.18 PCIe Secondary Header Log 3 Register Register name: PCIE_SEC_HL3 Register offset: 0x144 Reset value: 0x0000_0000 Bits 31:24 TRAN_ADD[31:24] 23:16 TRAN_ADD[23:16] 15:08 TRAN_ADD[15:08] 07:00 TRAN_ADD[07:00] Bits Name Description Type Reset value 31:00 TRAN_ADD[31:00] Transaction Address...
Page 217: Replay Latency Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.20 Replay Latency Register Register name: REPLAY_LATENCY Register offset: 0x208 Reset value: 0x0000_0000 Bits 31:24 Reserved 23:16 Reserved 15:08 REPLAY_L REPLAY_LATENCY AT_EN 07:00 REPLAY_LATENCY Bits Name Description Type Reset value 31:16 Reserved Reserved REPLAY_LAT_EN...
Page 218: Ack/Nack Update Latency Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.21 ACK/NACK Update Latency Register Register name: ACKNAK_UPD_LAT Register offset: 0x20C Reset value: 0x0009_0009 Bits 31:24 UPDATE_ Reserved UPDATE_LATENCY LAT_EN 23:16 UPDATE_LATENCY 15:08 ACKNAK_ Reserved ACKNAK_LATENCY LAT_EN 07:00 ACKNAK_LATENCY Bits Name Description Type Reset value...
Page 219: N_Fts Register
14. Register Descriptions > Advanced Error Reporting Capability Registers 14.8.22 N_FTS Register Register name: N_FTS Register offset: 0x210 Reset value: 0x0000_0020 Bits 31:24 Reserved 23:16 Reserved 15:08 Reserved 07:00 N_FTS Bits Name Description Type Reset value 31:08 Reserved Reserved 07:00 N_FTS This register indicates the N_FTS count value to be 0x20...
Page 220 14. Register Descriptions > Advanced Error Reporting Capability Registers PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 221: Pcie And Serdes Control And Status Registers
14.9 PCIe and SerDes Control and Status Registers The following table outlines the PCIe SerDes and PCS layer registers. These registers are mainly for status reporting and testing. Caution should be taken when modifying any of these registers during normal operation. Any unused offset space should be treated as reserved. The SerDes Control and Status Registers must not be accessed if the SerDes is in reset nor when the reference clock is stopped.
Page 222: Pcie Per-Lane Transmit And Receive Registers
> PCIe and SerDes Control and Status Registers 14.9.2 PCIe Per-Lane Transmit and Receive Registers 14.9.3 PCIe Transmit and Receive Status Register This register reflects the default state of the SerDes transmit and receive control inputs at power-up. Its reset value depends on various inputs. When its accompanying override registers are used, however (see “PCIe Output Status and Transmit Override Register”...
Page 223: Pcie Output Status And Transmit Override Register
> PCIe and SerDes Control and Status Registers 14.9.4 PCIe Output Status and Transmit Override Register This register indicates the status of output signals. Its reset value depends on various inputs. The register also provides a method for overriding the value of TX_BOOST in the “PCIe Transmit and Receive Status Register”.
Page 224: Pcie Receive And Output Override Register
> PCIe and SerDes Control and Status Registers 14.9.5 PCIe Receive and Output Override Register This register provides a method for overriding the values of LOS_CTL, RX_EQ_VAL, and RX_ALIGN_EN in the “PCIe Transmit and Receive Status Register”. Register name: PCIE_RX_OVRD Register offset: 0x008 Reset value: Undefined Bits...
Page 225: Pcie Debug And Pattern Generator Control Register
> PCIe and SerDes Control and Status Registers 14.9.6 PCIe Debug and Pattern Generator Control Register This register controls the pattern generator in the SerDes. Register name: PCIE_DBG_CTL Register offset: 0x00C Reset value: 0x0000_0000 Bits Reserved PATO PATO TRIGGER_ MODE 15:08 Reserved 07:00...
Page 226: Pcie Pattern Matcher Control And Error Register
> PCIe and SerDes Control and Status Registers 14.9.7 PCIe Pattern Matcher Control and Error Register This register controls the pattern matcher in the SerDes. Register name: PCIE_PM_CTL Register offset: 0x02C Reset value: Undefined Bits OV14 COUNT COUNT 15:08 Reserved 07:00 Reserved SYNC...
Page 227: Pcie Ss Phase And Error Counter Control Register
> PCIe and SerDes Control and Status Registers 14.9.8 PCIe SS Phase and Error Counter Control Register This register holds the current MPLL phase selector value and information for the associated error counter in the SerDes. Register name: PCIE_SS_EC_CTL Register offset: 0x030 Reset value: Undefined Bits Reserved...
Page 228: Pcie Scope Control And Frequency Integrator Register
> PCIe and SerDes Control and Status Registers 14.9.9 PCIe Scope Control and Frequency Integrator Register Register name: PCIE_SCTL_FI Register offset: 0x034 Reset value: 0000_0000 Bits Reserved Reserved 15:08 Reserved FVAL 07:00 FVAL DTHR_F Reset Bits Name Description Type Value 31:14 Reserved Reserved...
Page 229: Pcie Clock Module Control And Status Registers
> PCIe and SerDes Control and Status Registers 14.9.10 PCIe Clock Module Control and Status Registers 14.9.11 PCIe Control and Level Status Register This register indicates the status of various control inputs. Its reset value depends on inputs. When its accompanying override register is used, however (see “PCIe Control and Level Override Register”),...
Page 230: Pcie Control And Level Override Register
> PCIe and SerDes Control and Status Registers 14.9.12 PCIe Control and Level Override Register The register provides a method for overriding the value of TX_LVL, LOS_LVL, and ACJT_LVL in the “PCIe Control and Level Status Register”. Register name: PCIE_CTL_OVRD Register offset: 0x428 Reset value: Undefined Bits...
Page 231: Table 39: Tx_Lvl Values
> PCIe and SerDes Control and Status Registers Table 39: TX_LVL Values (Continued) TX_LVL Value TX_LVL[0:4] Vdiff-pp (mV) 0x06 5'b00110 987.9 0x07 5'b00111 997.6 0x08 5'b01000 1007.2 0x09 5'b01001 1016.9 5'b01010 1026.6 5'b01011 1036.3 5'b01100 1046.0 5'b01101 1055.7 5'b01110 1065.4 5'b01111 1075.0 0x10...
Page 232 > PCIe and SerDes Control and Status Registers PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 233: Electrical Characteristics
Electrical Characteristics Topics discussed include the following: • “Absolute Maximum Ratings” • “Recommended Operating Conditions” • “Power Characteristics” • “Power Supply Sequencing” • “DC Operating Characteristics” • “AC Timing Specifications” • “AC Timing Waveforms” 15.1 Absolute Maximum Ratings Table 40: Absolute Maximum Ratings – PCI Symbol Parameter Minimum...
Page 234: Recommended Operating Conditions
15. Electrical Characteristics > Recommended Operating Conditions 15.2 Recommended Operating Conditions Table 42: Recommended Operating Conditions Symbol Parameter Minimum Maximum Units Notes 3.3V DC I/O supply voltage DD_PCI 3.3V DC PCIe supply voltage DDA_PCIE 1.05V DC core supply voltage 0.945 1.155 1.05V DC PCIe digital supply voltage 0.945...
Page 235: Power Supply Sequencing
15. Electrical Characteristics > Power Supply Sequencing Table 43: PEB383 Power Dissipation (Continued) Typical Device ASPM Link Power Power State State Bridge Activity D3hot Power Saving Mode. All PCI Clocks 0.128 0.148 Gated D3cold Power Removed 0.060 0.069 Table 44: PEB383 Power Dissipation per Supply Typical 1.0V_A 3.3V_A...
Page 236: Ac Timing Specifications
15. Electrical Characteristics > AC Timing Specifications Table 45: DC Operating Characteristics (Continued) Symbol Parameter Condition Minimum Maximum Units Notes 3.3 CMOS Input Low -0.5 IL_33 Voltage Input Pin Capacitance IN_PCI Clock Pin Capacitance CLK_PCI PCI_CLK Input Pin Inductance IN_PCI Clock Pin Inductance CLK_PCI PCI_CLK...
Page 237: Pcie Differential Transmitter Output Specification
15. Electrical Characteristics > AC Timing Specifications 15.6.2 PCIe Differential Transmitter Output Specification The following table lists the specification of parameters for the differential output of the PCIe lanes. Table 47: PCIe Differential Transmitter Output Specification Symbol Parameter Min. Nom. Max.
Page 238 15. Electrical Characteristics > AC Timing Specifications Table 47: PCIe Differential Transmitter Output Specification (Continued) Symbol Parameter Min. Nom. Max. Units Comments Absolute Delta of DC | <= TX_CM-LINE TX-CM-DC-D+ TX-CM-DC-D+ Common Mode 25mV -DELTA Voltage between D+ = DC of |V TX-CM-DC-D+ (AVG)
Page 239 15. Electrical Characteristics > AC Timing Specifications Table 47: PCIe Differential Transmitter Output Specification (Continued) Symbol Parameter Min. Nom. Max. Units Comments Lane-to-Lane Output -2.8 500 + 2 UI Static skew between any two TX-SKEW Skew Transmitter Lanes within a single Link AC Coupling Capacitor All Transmitters must be AC coupled.
Page 240: Figure 40: Transmitter Eye Voltage And Timing Diagram
15. Electrical Characteristics > AC Timing Specifications Figure 40: Transmitter Eye Voltage and Timing Diagram 1. This diagram is an excerpt from PCI Express Base Specification (Revision 1.1), Revision 1.1, “Transmitter Compliance Eye Diagrams,” page 225. PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 241: Pcie Differential Receiver Input Specifications
15. Electrical Characteristics > AC Timing Specifications 15.6.3 PCIe Differential Receiver Input Specifications The following table lists the specification of parameters for the differential output of the PCIe lanes. Table 48: PCIe Differential Receiver Input Specifications Symbol Parameter Min. Nom. Max.
Page 242 15. Electrical Characteristics > AC Timing Specifications Table 48: PCIe Differential Receiver Input Specifications (Continued) Symbol Parameter Min. Nom. Max. Units Comments Electrical Idle Detect = 2*|V RX-IDLE-DET-DIFFp RX-IDLE-DET-DIFFp RX-D+ Threshold RX-D- Measured at the package pins of the Receiver. Unexpected Electrical An unexpected Electrical Idle RX-IDLE-DET-DIFF-E...
Page 243: Figure 41: Minimum Receiver Eye Timing And Voltage Compliance Specification
15. Electrical Characteristics > AC Timing Specifications Figure 41: Minimum Receiver Eye Timing and Voltage Compliance Specification 1. This diagram is an excerpt from PCI Express Base Specification, Revision 1.1, “Differential Receiver (RX) Input Specifications,” page 230. Integrated Device Technology, Inc. PEB383 User Manual Confidential - NDA Required July 25, 2011...
Page 244: Reference Clock
15. Electrical Characteristics > AC Timing Specifications 15.6.4 Reference Clock The following table lists the PEB383’s electrical characteristics for the differential SerDes reference clock input (PCIE_REFCLK_n/p). Table 49: Reference Clock (PCIE_REFCLK_n/p) Electrical Characteristics Symbol Parameter Min. Typ. Max. Unit Notes Differential Input Voltage DIFF Differential Input...
Page 245: Boundary Scan Test Signal Timing
15. Electrical Characteristics > AC Timing Specifications 15.6.5 Boundary Scan Test Signal Timing The following table lists the test signal timings for the PEB383. Table 50: Boundary Scan Test Signal Timings Symbol Parameter Units Notes JT_TCK Frequency JT_TCK High Time Measured at BSCH 1.5V,...
Page 246: Ac Timing Waveforms
15. Electrical Characteristics > AC Timing Waveforms Table 51: Reset Timing (Continued) Symbol Parameter Units Notes PCI_CLK clock stable to de-assertion of device reset Power-up strapping hold from de-assertion of device reset Assertion of reset to outputs tri-state 15.7 AC Timing Waveforms This section contains AC timing waveforms for the PEB383.
Page 247: Figure 44: Output Timing Measurement Waveforms
15. Electrical Characteristics > AC Timing Waveforms Figure 44: Output Timing Measurement Waveforms test tfall OUTPUT DELAY FALL OUTPUT DELAY RISE Vtrise OUTPUT FLOAT Figure 45: PCI T Rising Edge AC Test Load OV (max) Test Point Output 25Ω 10pF Figure 46: PCI T Falling Edge AC Test Load OV (max)
Page 248: Figure 47: Pci Tov (Min) Ac Test Load
15. Electrical Characteristics > AC Timing Waveforms Figure 47: PCI T AC Test Load OV (min) CC33 Test 1KΩ Point Output 1KΩ 10pF PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 249: Packaging
Packaging Topics discussed include the following: • “Pinouts and Mechanical Diagrams” • “Thermal Characteristics” • “Moisture Sensitivity” Integrated Device Technology, Inc. PEB383 User Manual Confidential - NDA Required July 25, 2011...
Page 250: Pinouts And Mechanical Diagrams
16. Packaging > Pinouts and Mechanical Diagrams 16.1 Pinouts and Mechanical Diagrams 16.1.1 QFP Package Pinout VSS_IO PCI INTDn PCI_AD[0] PCI_CLKO[4] PCI_AD[2] PCI_INTCn PCI_AD[1] PCI_INTBn PCI_AD[3] VDD_PCI PCI AD[4] PCI INTAn VDD_PCI PCI_PMEn JTAG_TDI PCI AD[5] PCI_AD[6] JTAG_TDO TOP VIEW PCI_AD[7] JTAG_TMS PCI_CBEn[0] JTAG_TRSTn...
Page 251: Qfp Package Drawing
16. Packaging > Pinouts and Mechanical Diagrams 16.1.2 QFP Package Drawing Integrated Device Technology, Inc. PEB383 User Manual Confidential - NDA Required July 25, 2011...
Page 252 16. Packaging > Pinouts and Mechanical Diagrams 16.1.2.1 QFP Package Drawing — Page 2 PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 253: Qfn Package Pinout
16. Packaging > Pinouts and Mechanical Diagrams 16.1.3 QFN Package Pinout Integrated Device Technology, Inc. PEB383 User Manual Confidential - NDA Required July 25, 2011...
Page 254: Qfn Package Drawing
16. Packaging > Pinouts and Mechanical Diagrams 16.1.4 QFN Package Drawing PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 255 16. Packaging > Pinouts and Mechanical Diagrams 16.1.4.1 QFN Package Drawing — Page 2 Integrated Device Technology, Inc. PEB383 User Manual Confidential - NDA Required July 25, 2011...
Page 256: Thermal Characteristics
16. Packaging > Thermal Characteristics 16.2 Thermal Characteristics Heat generated by the packaged silicon must be removed from the package to ensure the silicon is maintained within its functional and maximum design temperature limits. If heat buildup becomes excessive, the silicon temperature may exceed the temperature limits. A consequence of this is that the silicon may fail to meet the performance specifications and the reliability objectives may be affected.
Page 257: Table 53: Thermal Specifications - 33Mhz
16. Packaging > Thermal Characteristics Table 53: Thermal Specifications — 33MHz Power estimates are based on simulations — 0.511 W @ 33MHz Package Parameter Air Flow Unit 0 m/s 1 m/s 2 m/s QFP — EM128 θ 43.9 36.9 33.7 Max @ T AMB =85°C Max @ T AMB =70°C θ...
Page 258: Moisture Sensitivity
16. Packaging > Moisture Sensitivity Example of Thermal Data Usage θ Based on above data and specified conditions, the Junction temperature of the PEB383 with a 0 m/s airflow can be determined using the following formula: θ P + T JA * Where: •...
Page 259: Ordering Information
Ordering Information Legend A = Alpha Character N = Numeric Character Product Operating Temp Tape & Device Protocol Product Range Reel Family Revision Voltage Detail Tape & Reel Commercial Temperature Blank (0°C to +70°C Ambient) 132 132-ball QFN 132 132-ball QFN, Green 128 128-ball TQFP 128 128-ball TQFP, Green ZA revision...
Page 260 17. Ordering Information > PEB383 User Manual Integrated Device Technology, Inc. July 25, 2011 Confidential - NDA Required...
Page 261: Glossary
Glossary Address decode window The address range defined by a device’s base address registers when operating in non-transparent addressing mode. If a transaction address on the bus falls within a device’s address decode window, the device claims the transaction. Base and limit register A configuration register that stores memory or I/O address decode information in a device.
Page 262 Glossary Message A TLP used to communicate information outside of the memory, I/O, and configuration spaces. Message TLPs are always posted, and may or may not contain data. Non-transparent This type of addressing is used by a PCI bridging device to isolate the primary address map from the addressing secondary address map.
Page 263: Index
Index numeric conventions symbols downstream data path non-transparent registers absolute maximum ratings AC timing PCI Interface ECRC error AC timing specifications EEPROM controller AC timing waveforms EEPROM device address decoding EEPROM image I/O memory error handling memory-mapped I/O PCIe non-transparent exclusive access prefetchable memory advanced error reporting capability registers...
Page 264 Index mechanical diagram memory-mapped I/O addressing TAP controller message signaled interrupts (MSI) target-abort errors message signaled interrupts (MSI-X) TCK signal message transactions TDI signal message-based interrupts TDO signal enhanced message signaled interrupts thermal characteristics message signaled interrupts timeout errors timing waveforms TMS signal non-transparent addressing transaction forwarding...

IDT 89HPEB383 User Manual

About this Document

1 Functional Overview

2 Signal Descriptions

3 Data Path

4 Addressing

5 Configuration Transactions

6 Bridging

7 PCI Arbitration

8 Interrupt Handling

9 Error Handling

10 Reset and Clocking

11 Power Management

12 Serial EEPROM

13 Jtag

14 Register Descriptions

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Summary of Contents for IDT 89HPEB383