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LDT & PCI Bus Control (Press Enter)
Scroll to this item and press <Enter> to view the following screen:
Upstream LDT Bus Width
Downstream LDT Bus Width
LDT Bus Frequency
PCI Master 0 WS Write
PCI2 Master 0 WS Write
PCI Post Write
PCI2 Post Write
PCI Delay Transaction
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
F5:Previous Values
Upstream/Downstream LDT Bus Width (16 bit)
The LDT bus (Lighting Data Transport) is the bus between the North and South Bridge, and boosts
no less than 6.4 GB/s on a 16 bit upstream and 16 bit downstream data flow.
LDT Bus Frequency (1GHz)
This option allows you to specify the maximum operating frequency for the LDT transmitter clock.
PCI/2 Master 0 WS Write (Enabled)
When enabled, writes to the PCI bus are executed with zero wait states, providing faster data
transfer.
PCI/2 Post Write (Enabled)
When enabled, writes from the CPU to PCU bus are buffered, to compensate for the speed
differences between the CPU and PCI bus. When disabled, the writes are not buffered and the
CPU must wait until the write is complete before starting another write cycle.
PCI Delay Transaction (Disabled)
The motherboard's chipset has an embedded 32-bit post write buffer to support delay transactions
cycles. Select Enabled to support compliance with PCI specification version 2.1.
Press <Esc> to return to the Advanced Chipset Features page.
VLink Data Rate (8X)
This option allows you to select the data transfer rate between the Northbridge and Southbridge
chipsets.
Init Display First (PCI slot)
Use this item to specify whether your graphics adapter is installed in one of the PCI slots or is
integrated on the motherboard
Phoenix-AwardBIOS CMOS Setup Utility
LDT & PCI Bus Control
[16bit]
Menu Level
[16bit]
[1 GHz]
[Enabled]
[Enabled]
[Enabled]
[Enabled]
[Disabled]
F6:Fail-Safe Defaults
F7:Optimized Defaults
Using BIOS
Item Help
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