Lsi Pin Description - Yamaha EMX3000 Service Manual

LSI PIN DESCRIPTION

ZFX-2 (XY297A00) CPU
PIN
NAME I/O
No.
1 ED2 I/O
2 ED3 I/O
3 ED4 I/O
External Memory and I/O Data Bus
4 ED5 I/O
5 ED6 I/O
6 ED7 I/O
7 VSS S Ground
8 VDD S Power Supply
9 CLKM0 I
Clock Mode
10 CLKM1 I
CLKM0
CLKM1
11 TMS I
TAP(Test Access Port) Mode Select
12 TDI I
TAP Data Input
13 TCK I TAP Clock
14 CLKIN I Master Clock
15 VSS S
Ground
16 VDD S
Power Supply
17 CLKO O Machine Clock Output
18 EA12/ED8 I/O
19 EA13/ED9 I/O
External SRAM and ROM Address Bus/
20 EA14/ED10 I/O
External DRAM and I/O Data Bus
21 EA15/ED11 I/O
22 VSS S Ground
23 VDD S
Power Supply
24 EA16/ED12 I/O
25 EA17/ED13 I/O External SRAM and ROM Address Bus/
26 EA18/ES14 I/O External DRAM and I/O Data Bus
27 EA19/ED15 I/O
28 EA4/ED16 I/O
29 EA5/ED17 I/O
External Memory Address Bus/ External I/O
30 EA6/ED18 I/O Data Bus
31 EA7/ED19 I/O
32 VSS S
Ground
33 VDD S
Power Supply
34 EA8/ED20 I/O
35 EA9/ED21 I/O External Memory Address Bus/ External I/O
36 EA10/ED22 I/O
Data Bus
37 EA11/ED23 I/O
38 TEST0 I
39 TEST1 I
Test Mode Control
40 TEST2 I
41 TEST3 I
42 /BIO I
Separate Control Input
43 /INT1 I Interrupt 1
44 ARBC1 I Audio Data Receive Unit 1 bit Clock
45 ARBC2 I
Audio Data Receive Unit 2 bit Clock
46 AX1 O
Audio Data Transmitt Unit 1 Data Output
47 AX2 O Audio Data Transmitt Unit 2 Data Output
48 AX3 O Audio Data Transmitt Unit 3 Data Output
49 VSS S
Ground
50 VDD S
Power Supply
51 HX/SDA I/O/Z Host Interface Data Output/I2C Bus Data
52 /EMPTY O/Z CMEM Update Buffer and HR Resistor Empty Flag Output
FUNCTION
1 3 6 PLL BYPASS
0 1 0 1
0 0 1 1
PIN
NAME I/O
No.
53 AXLR2 I
Audio Data Transmitt Unit 2/3 Left and
Right Channel Frame Frequency Signal
54 AR1 I Audio Data Receive Unit 1 Data Input
55 AR2 I Audio Data Receive Unit 2 Data Input
56 HRBCK/SA0 I
Host Interface Receive Clock / I2C Bus Address 0
57 HR/SA1 I
Host Interface Data Input/ I2C Bus Address 1
58 HRS/SA2 I H o s t I n t e r f a c e R e c e i v e D a t a F r a m e
Frequency Signal/ I2C Bus Address 2
59 VSS S
Ground
60 VDD S
Power Supply
61 HXBCK/SCL I Host Interface Transmitt Clock/ I2C Bus Clock
62 HXS/SA3 I H o s t I n t e r f a c e T r a n s m i t t D a t a F r a m e
Frequency Signal/ I2C Bus Address 3
63 /CS/SA4 I
Host Interface Chip Select/ I2C Bus Address 4
64 HBCKS/SA5 I
HRBCK/HXBCK Active Edge Select/ I2C Bus Address 5
65 I2CSEL I Host Interface Mode Select
66 VSS S Ground
67 VDD S
Power Supply
68 AXBC1 I
Audio Data Transmitt Unit 1 bit Clock
69 AXBC2 I Audio Data Transmitt Unit 2/3 bit Click
70 AXLR1 I Audio Data Transmitt Unit 1 Left and Right
Channel Frame Frequency Signal
71 DIVS O
Machine Clock Output then 8 min.
72 /LAV O Ruch ALU Overflow Frag Output
73 /LMV O Ruch MAC Overflow Frag Output
74 /DRDY O/Z
Host Interface Transmitt Data Ready Frag Output
75 EMU0 I/O/Z
Emurator Interrupt 0
76 EMU1 I/O/Z Emurator Interrupt 1
77 TDO O/Z TAP(Test Access Port) Data Output
78 DIV512 O Machine Clock then512 min.
79 ARLR1 I
Audio Data Receive Unit 1 Left and Right
Channel Frame Frequency Signal
80 ARLR2 I Audio Data Receive Unit 2 Left and Right
Channel Frame Frequency Signal
81 HDIR/SA6 I
Host Interface Data Format Select/ I2C Bus Address 6
82 SEL5V3V I
Input Level Control
83 /MUTE I Mute Control
84 /TRST I TAP(Test Access Port) Reset
85 /RS I
Hardware Reset
86 VSS S
Ground
87 VDD S Power Supply
88 /IOE O External I/O Enable
89 /RAS/SRCS O
External DRAM Low Address Strove/External
SRAM Chip Select
90 /CAS/SROE O
External DRAM Culumn Address Strove/External
SRAM Output Enable
91 /ROME O External ROM Enable
92 /WE O
External Memory and I/O Wright Enable
93 EA0 O
94 EA1 O
External Memory and I/O Address Bus
95 EA2 O
96 EA3 O
97 VSS S
Ground
98 VDD S Power Supply
99 ED0 I/O
External Memory and I/O Data Bus
100 ED1 I/O
EMX3000
DSP: IC105
FUNCTION
17