Squelch Control; Transmit Signal Path; Pll Frequency Synthesizer - Standard Horizon HX600S Service Manual

Circuit Description
Demodulated audio is output from pin 9 of the Narrow
IF IC through narrow mute analog switch Q1047 before
de-emphasis at Q1053.
The demodulated audio signal from the Q1063 passes
through a band-pass filter and squelch gate Q1029
(NJM12902V).
The resulting audio is amplified by AF amplifier Q1009
and output through MIC/EAR jack J1001 to internal speak-
er or an external earphone.

2. Squelch Control

Signal components in the neighborhood of 15 kHz con-
tained in the discriminator output pass through an active
band-pass filter composed of R1226, R1230, R1239, C1176,
C1182 and the operational amplifier between pins 7 and
8 within IF IC Q1063. They are then rectified by D1032
and D1034 (DA221) to obtain a DC voltage correspond-
ing to the level of noise. This voltage is input to pin 16 of
CPU Q1026 (LC87F5BP8A-F56G2), which compares the
input voltage with a previously set threshold. When the
input voltage drops below the threshold, normally due to
the presence of a carrier, turning on squelch gate Q1029
and allowing any demodulated audio to pass. At the same
time, Q1002 and/or Q1004 and/or Q1006 goes on, caus-
ing the BUSY/TX lamp D1009 (SDDF01000A) to light.

3. Transmit Signal Path

Transmit/Receive Switching
Closing PTT switch S1002 pulls the base of Q1008
(DTA144EE) low, causing the collector to go high. This
signal is input to pin 22 (PTT) of CPU Q1026, allowing
the CPU to recognize that the PTT switch has been pushed.
When the CPU detects closure of the PTT switch, pin 31
(TX/RX) goes high. This control signal is switches Q1083
(UMD5N). At the same time, PLL division data is input to
PLL IC Q1027 (MB15A01PFV1) from the CPU, to disable
the receiver power saver. Also, switching Q1076 (UMB3N)
to disable the receiver circuits. Then causing the red side
of BUSY/TX lamp D1009 to light.
Modulation
Voice signal input from either built-in microphone
MC1001 (SKB-2244S) or external jack J1001 is pre-em-
phasized by C1020 and R1034, and processed by micro-
phone amplifier Q1010 (NJM12902AV), IDC (instanta-
neous deviation control) circuit to prevent over-modula-
tion, and active low-pass filter.
Transmission
Modulating audio passes through deviation setting D/A
converter Q1014 to MOD of the VCO. This signal is ap-
plied to varactor D1016 (HSC277) in the tank circuit of
VCO Q1034 (2SC5555), which oscillates at the desired
8
transmitting frequency. The modulated VCO signal is
buffered by amplifier Q1040 (2SC5555) and delivered
through T/R diode switch D1026. The modulated low-lev-
el transmit signal from the VCO is applied to amplifier
Q1048 (2SC5226-5). The modulated transmit signal from
the VCO is amplified by Q1056 (2SK3475) and RF power
amplifier Q1066 (2SK3476) up to 5 W. The RF output
passes through TX diode switch D1048. RF output is
passed by T/R switch and low-pass filter to suppress har-
monics and spurious products before output to the an-
tenna at the antenna terminal.

4. PLL Frequency Synthesizer

PLL IC Q1027 consists of a data shift register, reference
frequency divider, phase comparator, charge pump, in-
termittent operation circuit, and band selector switch.
Serial PLL data from the CPU is converted into parallel
data by the shift register in the PLL IC and is latched into
the comparative frequency divider and reference frequen-
cy divider to set a frequency dividing ratio for each. An
11.7 MHz reference signal produced by X1001 is input to
REF pin 1 of the PLL IC. The internal reference frequency
divider divides the 11.7 MHz reference by 2,340 (or 1,872)
to obtain a reference frequency of 5 kHz (or 6.25 kHz),
which is applied to the phase comparator. Meanwhile, a
sample of the output of VCO Q1040 is input to the PLL
IC, where it is frequency-divided by the internal compar-
ative frequency divider to produce a comparative frequen-
cy also applied to the phase comparator. The phase com-
parator compares the phase between the reference fre-
quency and comparative frequency to output a pulse cor-
responding to the phase difference between them. This
pulse is input to the charge pump, and the output from
the charge pump passes through a loop filter composed
of L1005, R1142, C1098, R1143, C1104, R1151, and C1110,
which convert the pulse into a corresponding smoothed
varactor control voltage (VCV). The VCV is applied to
varactor D1015 (1SV325) in the VCO tank circuit to elim-
inate phase difference between the reference frequency
and comparative frequency, and so locking the VCO os-
cillation frequency to the reference crystal. The VCO fre-
quency is determined by the frequency-dividing ratio sent
from the CPU to the PLL IC. During receiver power save
operation, the PLL circuit operates intermittently to re-
duce current consumption, for which the intermittent op-
eration control circuit reduces the lock-up time.