Sharp FACSIMILE FO-4500 Service Manual page 95

(4) Reading process and mechanical control block
1) Reading process block
The reading block is composed of the following blocks.
1
CCD drive block (IC15: LZ9FJ37A)
2
Analog process block
• Analog LSI(IC22: TLS1049)
• Tr.C/R etc
3
Binary coding block/read data control block (IC15: LZ9FJ37A)
The details of each block are described as follows.
a) CCD drive block
The clock signal necessary for CCD drive is supplied from gate array
(A) to CCD.
Hereafter, the clocks are outlined.
• φT -- Line synchronous signal
• φ1/φ2 --- Transmission clock
b) Analog process block
The analog video signal supplied from CCD PWB is directly supplied
to the analog LSI.
On the other hand, as the reference level (reference voltage) of A/D
conversion, the peak voltage of the video signal detected in the peak
hold circuit is supplied to the A/D conversion block in the stan-
dard/fine/super fine mode and the fixed voltage is supplied to the
block in the half tone mode. After the offset part is cut in the analog
LSI, 7-bit digital video signal is supplied to the gate array by using the
integrated 7-bit high speed A/D converter according to the A/D con-
version clock output from the gate array.
c) Binary coding block/read data control block
It is composed of the processing circuit (IC15: LZ9FJ37A) which inte-
grates various binary coding algorithms and the reading line memo-
ries (IC20, IC21: LH5268TH10) which record necessary data. The
digital video signal input in 7 bits is judged as 2 values (black(1) and
white (0), and the data is transmitted to the gate array (B) (IC16:
LR38292) in the serial mode and is stored in the page memory.
The contents binary-coded here are as follows.
• Shading compensation
• Half tone process (error diffusion process)
• MTF compensation
2) Mechanical control block
The mechanical control block is mainly composed of the gate array
(A) (IC15: LZ9FJ37A) to control the following.
(a) Sending motor control
The revolution speed and timing of the sending motor are controlled
to output the control signals to the motor driver (IC13, IC17).
(b) End stamp and LED lamp control
On/off of the end stamp and LED lamp is controlled with the software.
(5) Gate array (A) block
This block is mainly composed of the gate array (A) (IC15:
LZ9FJ37A), and has the following functions.
1
Mapper
Mapping is executed in the memory area of the memories, gate
array (B), modem and CODEC.
2
Reading process
Refer to 1) Reading process block of 2-4 Reading and mechanical
control block.
3
Mechanical control block
Refer to 2) Mechanical control block of 2-5 Reading and mechani-
cal control block.
4
IC interface for clock
Writing and reading to IC (IC106: NJU6355E) for clock is executed
in the clock-synchronous type serial transfer mode.
5
TEL/LIU control port
6
PC interface
• I/O port control (communication is done with main CPU.)
• Detection of communication speed with AT command monitor
6
Generation of alarm sound and ringer sound
The keys on the operation panel are pressed to respectively gen-
erate the key input sound, alarm sound and ringer sound.
7
Speaker sound control
Output of the circuit monitor sound, key input sound, alarm sound
and ringer sound is switched with the analog switch (IC110:
BU4053), and the sound volume is controlled with the analog
switch (IC105: NJU4051).
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FO-4500H