Chapter 5. Circuit Description; Circuit Description; Circuit Description Of Control Pwb - Sharp FACSIMILE FO-4500 Service Manual

CHAPTER 5. CIRCUIT DESCRIPTION

[1] Circuit description

1. General description
In this machine, the facsimile control block except the printer control
is mainly composed of the units shown in Fig. 1.
2. PWB configuration
CCD
PWB
LINE
HOOK
TEL/LIU
CONTROL PWB
SWITCH
PWB
PWB
OPERATION PANEL
PWB
1) Control PWB
The control PWB controls all the other operations except the printing
operation of the printer.
2) TEL/LIU PWB
The TEL/LIU PWB controls the I/F telephone function of the circuit
with the control signals from the control PWB.
3) CCD PWB
CCD PWB converts the image of the sending or copying draft into the
photoelectric signals and transmits the signals to the control PWB.
4) Operation panel PWB
The operation panel PWB detects the key input, turns on and off LED
and displays LCD according to the control signals from the control
PWB.
5) Power supply PWB
DC voltages (+5V, +12V, +24V) are produced from AC230-240V, and
are supplied to the printer unit and control PWB unit.

[2] Circuit description of control PWB

1. General description
The control PWB is composed of the following blocks.
1
Main control block
2
Image memory block
3
Modem block
4
Reading process and mechanical control block
5
Gate array (A) block
6
Gate array (B) block
7
CODEC block
8
Page memory block
9
Driver block
AC CORD
POWER SUPPLAY PWB
PRINTER
UNIT
RS232C
I/F PWB
Fig. 1
2. Description of each block
(1) Main control block
The main control block uses RISC microprocessor HD6477021X20 as
CPU, being composed of ROM (1 MByte) and DRAM (512 KByte).
1) HD6477021X20 (IC12): pin-100, QFP (main CPU)
The device is a microprocessor which integrates the peripheral func-
tions, using CPU of 32-bit RISC type as the core. In the instrument,
the following peripheral functions are mainly used.
1
ROM of 32 KByte and RAM of 1 KByte are integrated.
A part of programs are stored in the integrated ROM.
2
DMA controller (4 channels are provided, and 2 channels alone
are used.)
ch.0: Used to transmit image data between CODEC (HD813201F)
and DRAM(IC14).
ch.3: Used to transmit image data between CPU and
DRAM(IC14).
3
Clock-synchronous type serial communication interface Com-
mands and statuses are communicated with PCU.
4
Start-stop synchronous type serial communication interface Used
for PC interface of RS232C system.
5
Interruption
IRQ2: Interruption request from gate array (A) (LZ9FJ37A)
IRQ3: Interruption request from gate array (B) (LR38292)
IRQ4: Interruption request from CODEC (HD813201F)
IRQ6: Interruption request from modem (R144EFXL)
IRQ0, IRQ1, IRQ5, IRQ7: Not used.
NMI : Not used.
6
DRAM controller
Addressing to DRAM(IC14) of the system and control and refresh
control of RAS and CAS signals are executed.
7
Timer and watch dog timer
8
General-purpose I/O port
Control of TEL/Liu and control of analog process of read signals
are executed.
9
Clock oscillation
Ceramic oscillator of 19.66 MHz is connected for operation of
19.66 MHz.
2) 27C040 (IC1,5): pin-32, DIP (ROM)
Programs are stored in two 4 Mbit ROM.
3) HM514260 (IC7): pin-40, SOJ (DRAM)
Used as the system memory of main CPU and transmission buffer of
communication.
4) NJU6355E (IC106): pin-8, SOP (Real time clock IC)
It is oscillated with the quartz oscillator of 32.768 kHz, and the clock
and calendar functions are provided. Even if the power supply of the
main body is turned off, it is backed up with lithium battery. This
device executes the clock-synchronous type serial communication
with the gate array (A), and CPU can know the time and date through
the gate array (A).
5 – 1
FO-4500H