Sharp LC-37D90U Service Manual page 73

2.16. VHiTC6384AF1EQ (ASSY: IC8702)
SD_CARD_CONTROLER
• Pin Function [VHiTC6384AF1EQ (ASSY: IC8702)]
Pin No. Pin Name
Host interface
76 #CS
98, 97, 94, A [7:0]
93, 88, 85,
82, 77
13, 11, 10, D [15:1]
8, 4, 2, 1,
99, 95, 89,
83, 81, 75,
74, 70, 68
67 #RE
100 #WE
7 BE1
12 BE0
66 BEPOL
86 #ACK
87 #RQ
62 ASYNC
79 MCLK
6 MCLK2
91 #RESET
SD CARD interface
50 SDCLK
38 SD1CMD
36, 37, 42, SD1DAT [3:0]
45
47 #SD1CD
41 SD1WP
39 SD2CMD
22 SD2DAT3
24 SD2DAT2
30 SD2DAT1
34 SD2DAT0
27 #CD2
16 SD2WP
Smart Media interface
25 #SMUSE
34 #FCE
35 FCLE
23 FALE
24 #FRE
30 #FWE
17, 18, 20, FD [7:0]
21, 31, 32,
44, 46
29 #FBSY
14 #FWP
49 #EJECTIN
56 #EJECTOUT
27 (#CD2)
39 #FWPSD
DSP interface
57 ACCLK
55 #ACREQ
52 ACDATA
54 ACVALID
Other
73 DIP1
72 DIP0
71 LED3
I/O
I Chip select (accessible in #CS= "0").
I Address bit 7-0.
I/O Data bit [15:0].
I Read enable. The content of the register is output to D [15:0] when making it to "0".
I Write enable. When "0" is connected by three clocks, D [15:0] value is written in the register.
I Byte enable. Most Significant Byte becomes accessible at BE1=BEPOL.
I Byte enable. Least Significant Byte becomes accessible at BE0=BEPOL.
I Polarity setting of BE [1:0].
O Acnorigge signal when register is accessed.
O Interrupt output.
I Change of method in host interface.
I Main clock.
I SD card detection clock.
I Main reset.
O SD clock. Slot 1 and 2 using combinedly.
I/O SD command output. Response input (slot 1).
I/O SD data. Bit [3:0] (Slot1).
I SD detection input (Slot1).
I SD write-protection input (Slot1).
I/O SD command output. Response input (slot 2). #FWPSD and sharing.
I/O SD data. Bit3 (Slot2).
I/O SD data. Bit2 (Slot2). #FRE and sharing.
I/O SD data. Bit1 (Slot2). #FWE and sharing.
I/O SD data. Bit0 (Slot2). #FCE and sharing.
I SD detection input.
I SD write-protection input (Slot2).
I When Smart Media is used for slot 2, it is assumed, "0".
O Smart Media chip enable. SD2DAT0 and sharing.
O Smart Media command latch enable.
O Smart Media address latch enable.
O Smart Media Read enable. SD2DAT0 and sharing.
O Smart Media Write enable. SD2DAT1 and sharing.
I/O Smart Media data. Bit [7:0].
I Smart Media Ready/busy input signal.
O Smart Media write-protection output signal.
I Smart Media eject demand signal.
O Smart Media eject response signal.
I Smart Media card detection signal (SD2 and using combinedly).
I Smart Media write-protection seal detection signal (SD2CMD and using combinedly).
O A-CORE clock output ("0" fixed output).
I A-CORE request input (Please input "0" or "1" and stabilize potential).
O A-CORE data output ("0" fixed output).
O A-CORE effective horsepower ("0" fixed output).
I DIP input terminal for debugging.
I DIP input terminal for debugging.
O LED output terminal for debugging. It synchronizes with the LED bit of the SM_MCR register though it is
controlled by an internal register.
Pin Function
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LC-37D90U