Sharp LC-37D90U Service Manual page 50

LC-37D90U
Pin No.
L4 AVSS_OUTBUF
AD27, AG27 LVDS_VSSO
AE24 LVDS_VSSD
AF27 LVDS_VSSA
AH27 LVDS_VSSP
AH28 LVDS_VDDP
AF28 LVDS_VDDA
AE28 LVDS_VDDD
AD28, AG28 LVDS_VDDO
Ball Assignments for Reference Voltage.
M1 VREFP_1
M2 VREFN_1
V3 VREFP_2
V4 VREFN_2
Y3 VREFP_3
Y4 VREFN_3
R3 VREFP_4
R2 VREFN_4
Miscellaneous Ball Assignments.
A6 RESET
A7 INTN
C7 PWM0
D7 PWM1
C8 TESTMODE0
D8 TESTMODE1
A1, B2 GPIO 0, GPIO 1
F2, F3, E3, E2, E1, D1, AUDIO_P [11:0]
D2, D3, C3, C2, C1, B1
B13 MCU_CS
C13 MCU_CSN
LVDS Output Ball Assignments.
AK27 TCLK2M
AJ27 TCLK2P
AK25 TE2M
AJ25 TE2P
AK26 TD2M
AJ26 TD2P
AK28 TC2M
AJ28 TC2P
AB29 TA1P
AB30 TA1M
AC29 TB1P
AC30 TB1M
AD29 TC1P
AD30 TC1M
AF29 TD1P
AF30 TD1M
AG29 TE1P
AG30 TE1M
AE30 TCLK1M
AE29 TCLK1P
AK30 TA2M
AJ30 TA2P
AK29 TB2M
AJ29 TB2P
AH29 TF1P
AH30 TF1M
AJ24 TF2P
AK24 TF2M
Pin Name I/O
--- 3.3V ground for output.
--- LVDS out buffer ground.
--- LVDS Digital ground.
--- LVDS analog ground.
--- LVDS PLL ground.
--- LVDS PLL power.
--- LVDS analog power.
--- LVDS Digital power.
--- LVDS out buffer power.
--- ADC1 voltage reference +.
--- ADC1 voltage reference -.
--- ADC2 voltage reference +.
--- ADC2 voltage reference -.
--- ADC3 voltage reference +.
--- ADC3 voltage reference -.
--- ADC4 voltage reference +.
--- ADC4 voltage reference -.
I System reset powered by VDDH/VSS. RESET# forces the chip to a known state. This
pin should be tied to CPU reset.
I/O Interrupt signal (active low) powered by VDDH/VSS.
I/O General purpose I/O.
I/O General purpose I/O.
I Reserved (Connected to ground).
I Reserved (Connected to ground).
I/O Programmable general purpose I/O.
I/O Audio Data Input/Output.
I Initial LX setting for choosing I2C address & CPU bus Configuration.
I Initial LX setting for choosing I2C address & CPU bus Configuration.
O LVDS 2nd Channel Differential negative CLK out.
O LVDS 2nd Channel Differential positive CLK out.
O LVDS 2nd Channel Differential negative data out.
O LVDS 2nd Channel Differential positive data out.
O LVDS 2nd Channel Differential negative data out.
O LVDS 2nd Channel Differential positive data out.
O LVDS 2nd Channel Differential negative data out.
O LVDS 2nd Channel Differential positive data out.
O LVDS 1st Channel Differential positive data out.
O LVDS 1st Channel Differential negative data out.
O LVDS 1st Channel Differential positive data out.
O LVDS 1st Channel Differential negative data out.
O LVDS 1st Channel Differential positive data out.
O LVDS 1st Channel Differential negative data out.
O LVDS 1st Channel Differential positive data out.
O LVDS 1st Channel Differential negative data out.
O LVDS 1st Channel Differential positive data out.
O LVDS 1st Channel Differential negative data out.
O LVDS 1st Channel Differential positive CLK out.
O LVDS 1st Channel Differential negative CLK out.
O LVDS 2nd Channel Differential negative data out.
O LVDS 2nd Channel Differential positive data out.
O LVDS 2nd Channel Differential negative data out.
O LVDS 2nd Channel Differential positive data out.
O LVDS 1st Channel Differential positive CLK out.
O LVDS 1st Channel Differential negative CLK out.
O LVDS 2nd Channel Differential negative data out.
O LVDS 2nd Channel Differential positive data out.
Pin Function
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