Sharp LC-37D90U Service Manual page 51

2.10. RH-iXB375WJZZQ (ASSY: IC3501, 3502)
128Mbit GDDR SDRAM
• Block Diagram [RH-iXB375WJZZQ (ASSY: IC3501, 3502)]
• Pin Function [RH-iXB375WJZZQ (ASSY: IC3501, 3502)]
Pin No. Pin Name
11M, 12M CK, CK*1
12N CKE
2N CS
2M RAS
2L CAS
3L WE
2B, 13H, 2H, DQS0 -
13B DQS3
3B, 12H, 3H, DM0 - DM3
12B
I/O
I The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except DQ's and DM's that are sampled on
both edges of the DQS.
I Activates the CK signal when high and deactivates the CK signal when low.
By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode.
I CS enables the command decoder when low and disabled the command decoder when high.
When the command decoder is disabled,new commands are ignored but previous operations continue.
I Latches row addresses on the positive going edge of the CK with RAS low.
Enables row access & precharge.
I Latches column addresses on the positive going edge of the CK with CAS low.
Enables column access.
I Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
I/O Data input and output are synchronized with both edge of DQS.
DQS0 for DQ0 - DQ7, DQS1 for DQ8 - DQ15, DQS2 for DQ16 - DQ23,DQS3 for DQ24 - DQ31.
I Data In mask.
Data In is masked by DM Latency=0 when DM is high in burst write.
DM0 for DQ0 - DQ7, DM1 for DQ8 - DQ15, DM2 for DQ16 - DQ23, DM3 for DQ24 - DQ31.
Pin Function
5 – 35
LC-37D90U