Sharp LC-37D90U Service Manual page 70

LC-37D90U
Pin No. Pin Name
M13 GPIO2
N14 GPIO3
M14 GPIO4
B11 GPIO5
A10 GPIO6
A11 GPIO7
E10 GPIO8
B9 GPIO9
C7 GPIO10
Test Modes
D9 TEST_MODE
A2, A4, NO_CONNECT
C2, C3,
D3
Power and Ground Signals
F3, J5, VDD3.3
L2, K5,
M9, P14,
K11,
C14, B8
E3, E4, VDD1.5
N2, N3,
M12,
N13,
C13, C12
D1 PLLVDD1.5
C1 PLLVSS
G5, L4, VSS
N4, M7,
P11,
K13,
H14,
F13,
B12, C10
D2, D7, AVdd3.3
C6, A5
D6, B5, AVSS
D4, B2
Thermal Balls
E5, J6, ---
J7, J8,
J9, H6,
H7, H8,
H9, G6,
G7, G8,
G9, F6,
F7, F8,
F9
I/O
I/O GPIO. Output is controlled by the internal register. Input is monitored by internal register.
Can be used as watermark for also buffer 1.
I/O GPIO. Output is controlled by the internal register. Input is monitored by internal register.
For HSDI1 RX mode 8/9 (ceLynx Sync mode B compatible), it can be configured for HSDI1 AV out-
put.
I/O GPIO. Output is controlled by the internal register. Input is monitored by internal register.
Can be used as watermark for also buffer 2.
I/O GPIO. Output is controlled by the internal register. Input is monitored by internal register.
For HSDI2 RX mode 8/9 (ceLynx Sync mode B compatible), it can be configured for HSDI2 AV out-
put.
I/O GPIO. Output is controlled by the internal register. Input is monitored by internal register.
Can be used as watermark for any Async buffer.
I/O GPIO. Output is controlled by the internal register. Input is monitored by internal register.
Can be used as watermark for any Async buffer.
I/O GPIO. Output is controlled by the internal register. Input is monitored by internal register.
Can be used as watermark for any Async buffer.
I/O GPIO. Output is controlled by the internal register. Input is monitored by internal register.
Can be used as watermark for any Async buffer.
I/O GPIO. Output is controlled by the internal register. Input is monitored by internal register.
Can be used as watermark for any Async buffer.
I Used for internal TI testing. Should be tied to GND for normal operation.
--- These pins should not be connected to any signal, power, or ground.
--- 3.3V power supply for I/O power.
--- 1.5V power supply for core power.
--- 1.5V power supply for PHY PLL.
--- PLL ground.
--- Ground.
--- Analog VDD.
--- Analog Ground.
--- The center device balls are connected together, but electrically isolated from the device. For thermal
purposes, its recommended to connect these balls to a thermal dissipating ground plane (e.g. Vss).
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Pin Function