Circuit Description Of Control Pwb; General Description - Sharp FO-90 Service Manual

FO-90RA

[2] Circuit description of control PWB

1. General description

Fig. 2 shows the functional blocks of the control PWB, which is com-
posed of 5 blocks.
MAIN CONTROL BLOCK
(1) FAX ENGINE
(4) SRAM
Fig. 2 Control PWB functional block diagram
2. Description of each block
(1) Main control block
The main control block is composed of CONEXANT 1 chip fax engine
(FC200), ROM (2Mbit), SRAM (256kbit), FLASH MEMORY (512k × 8
bit) and Modem (FM209V).
Devices are connected to the bus to control the whole unit.
1) FC200 (IC3) : pin-144 QFP (FAX ENGINE)
2) FM209V (IC5) : pin-128 QFP (MODEM)
The FAX ENGINE Integrated Facsimile Controllers.
FC200, contains an internal 8 bit microprocessor with an external 16
Mbyte address space and dedicated circuitry optimized for facsimile
image processing and facsimile machine control and monitoring.
MIRQN
A[23:0]
D[7:0]
RDN
WRN
ROMCSN
CSN[1:0]
MCSN
SYNC
REGDMA
WAITN
RASN
CASN[1:0]
DWRN
TONE
GPIO[0]
GPIO[1]/SASTXD
GPIO[2]/SASRXD
GPIO[3]/SASCLK
GPIO[4]/CPCIN
GPIO[5]/SSCLK2
GPIO[6]/SSTXD2
GPIO[7]/SSRXD2
GPIO[8]/FWRN
GPIO[9]/FRDN
GPIO[10]/SSSTAT2
GPIO[11]/BE/SERINP
GPIO[12]/CS2N
GPIO[13]/CS3N
GPIO[14]/CS4N
GPIO[15]/CS5N
GPIO[16]/IRQ8
GPIO[17]/IRQ5N
GPIO[18]/IRQ9N
GPIO[19]/RDY/SEROUT
GPIO[20]/ALTTONE
SM[3:0]/GPO[7:4]
PM[3:0]/GPO[3:0]
+VREF
–VREF
START
VIN
CLK1
CLK1N
CLK2
VIDCTL0/FCS1N
VIDCTL1/FCS2N
(3) ROM
MODEM BLOCK
(2) MODEM
(5)
FLASH
MEMORY
EXTERNAL CPU BUS
GENERAL I/O
TONE/ALTTONE
GPIO
CALLING PARTY
CONTROL
AUTOBAUD
SYNC-ASYNC SASIF
SYNC SERIF 2
FLASH MEMORY IF
AUTOBAUD
SCANNER CONTROL & VIDEO PROCESSING
8-BIT PADC
CCD/CIS SCANNER
5 ms,A4/B4 LINES
SHADING CORRECTION(1:1,1:8)
DITHERING
MULTILEVEL B4-A4 REDUCTION
ERROR DIFFUSION
MTF
2.6kBYTE VIDEO RAM
PWR/GND TEST
3) 27C2000 (IC10): pin-32 DIP (ROM)
ROM of 2 Mbit equipped with software for the main CPU.
4) W24258S-70LE (IC6): pin-28 SOP (SRAM)
Line memory for the main CPU system RAM area and coding/decoding
process. Used as the transmission buffer.
Memory of recorded data such as daily report and auto dials. When the
power is turned off, this memory is backed up by the lithium battery.
5) KM29W040T (IC4): pin-44 TSOP (FLASH MEMORY)
A 512k × 8 bit NAND FLASH MEMORY to store the voice and image
data when using memory functions.
MC24 MEGACELL(8BIT DATA,24BIT ADDRESS)
BUS INTERFACE
DRAM CONTROL
INTERNAL & EXTERNAL BUS CONTROL
INTERNAL & EXTERNAL DECODE
DMA CONTROLLER
INTERNAL CPU BUS
BI-LEVEL RESOLUTION
CONVERSION
PROGRAMMABLE HARDWARE,ALTERNATE
REDUCTION &
EXPANSION
OPIF INPUTS
OPI[0]/GPIO[21]/SSRXD1
OPI[1]/GPIO[22]/SSSTAT1
OPI[2]/GPIO[23]/SSCLK1
OPI[3]/GPIO[24]
Fig. 3
5 – 2
MC24 CPU CONTROL IF
WATCHDOG TIMER
REAL TIME CLOCK
CRYSTAL OSCILLATOR
BATTERY BACK-UP CIRCUIT
INTERRUPT CONTROLLER
CPU BUS
OPERATOR PANEL IF
32 KEYS
8 LEDS
LCD MODULE
MOTOR POWER
CONTROL RINGER
SYNC SERIF 1
THERMAL PRINTER IF
T.4/T.6 CODEC
5 ms LINE TIME
MH,MR,MMR A4/B4 LINES
TPH ADC
COMPRESSION &
4 STROBE TPH
DECOMPRESSION
LATCHLESS TPH
EXTEMAL DMA I/F
DMA BUS
OPIF OUTPUTS
LEDCTL/GPO[16]
LCDCS/GPO[17]
OPO[0]/GPO[8]/SINPWR CTRL
OPO[1]/GPO[9]/PMPWR CTRL
OPO[2]/GPO[10]/RINGER
OPO[3]/GPO[11]
OPO[4]/GPO[12]/SSTXD1
OPO[5]/GPO[13]
OPO[6]/GPO[14]
OPO[7]/GPO[15]
WRPROTN
SYSCLK
TSTCLK
DEBUGN
RESETN
XIN
XOUT
PWRDWNN
BATRSTN
SEE
"OPIF
OUTPUTS"
BELOW
SEE
"OPIF
INPUTS"
BELOW
THADIN
PCLK
PDAT
PLAT
STRB[3:0]
STRBPOL