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HP 27130B
The events may be enabled or disabled by using the WCC, SF 21. The event interrupt is enabled by
setting the corresponding mask bit and disabled by clearing the bit.
If the interrupt mask for an event is disabled, you may poll for the event by using Read Card
Information (RCI), Subfunction (SF) 254.
See the paragraph "Event Block Description", for a detailed description of the event block format
returned to the host.
If all interrupt conditions are disabled, no asynchronous interrupts will occur.
SOLICITED EVENTS
The MUX will generate a solicited event upon completion of a speed sense operation. The event block
contains the "speed sense completed" event code, the baud rate which was detected, and the sense of
the parity bit in the carriage return character.
Because this event is solicited, it can be neither masked nor polled.
DIAGNOSTICS
The MUX self -test performs diagnostic tests to detect malfunctions. Self -test is executed 'offline'.
That is, it does not run concurrent with the standard MUX firmware.
It
is executed on a hardware
reset of the card following a CHANNEL I/O "Addressed Device Clear" (DCL/DEN) or "Reset" (RES)
assertion.
It
exercises the major components and data paths on the card. If no problems are found,
the card is made functional and the standard MUX firmware is invoked. If a hardware malfunction is
detected, the card is left disabled, indicating that self -test failed.
The following tests are performed by self-test:
* ROM test : To ensure that no bits have changed on the ROM (EPROM), a cyclic redundancy
check is done using the polynomial X**16+X**2+X+1. The test is performed in 4K segments to
ensure accuracy of the CRe.
* RAM test: RAM is checked for both stuck -at-O and stuck -at-1 conditions and address decoder
failures.
* ASYNC SIO Loop-back test: Verifies that the SIO can perform basic asynchronous transmit and
receive functions. If a loop-back hood is sensed, loop-back is performed using both the internal
and external line drivers.
*
eTC
test: Detects stuck -at faults in the data lines, system control, interrupt control (except CTC
1 and 2, which have no interrupt capability), and the four channel signals, for each CTC.
* SIC test: Checks the Backplane Interface Circuit (BIC) for functional faults. Checks for some
stuck -at faults in internal BIC registers. The BIC circuitry is tested using the internal loop-back
functionality built into it. Testing of I/O channel driver and receiver hardware external to the
BIC is not done by self -test. The combination of the host diagnostic and MUX loop-back support
in the 'standard' MUX firmware will exercise the host/MUX interface.
* MIC test: Checks the Memory Interface Circuit (MIC) for functional faults. The registers in the
MIC which can be read and written to are checked for stuck -at-1 and stuck -a t-O faults, and
both read and write DMA on both DMA channels are tested using SIO channel O. Some MIC
4-18
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