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HP 27130B
CTC (Counter Timer Circuit)
Three Z - 8 0 CTC circuits (U 5 1, lJ 61, U 71, see E 43, 7 -1) are used by the MUX card to provide baud
rate and real-time clocks.
The Z- 80 CTC circuit provides four independent counter/timer channels. Three of these timers
can supply outputs for other devices; the fourth channel can only cause an interrupt to the Z-80B
CPU.
Only the first CTC (CTC 0, U 51) is tied to the MUX card's daisy-chain interrupt structure
and is able to generate an interrupt to the Z-80B
cpu.
The fourth timer of CTC 0 is the real-
time clock for the card's firmware.
CTC 1 (U61) and CTC 2 (U71) are not tied to the interrupt daisy chain, and they are not allowed to
generate interrupts. These two CTCs are only used to generate baud rates.
The reason for
~liminating
CTC 1 and CTC 2 from the daisy-chain interrupt structure
IS
to con-
form to the timing requirements of the Z-80B
cpu
during lACK and RETI cycles. See the "Wait
State Circuit for Interrupt Acknowledge" paragraph for a timing analysis of the lACK and RETI
cycles.
The inputs of all four clock triggers (CLK/TRGO through CLK/TRG3) of all three CTCs are
driven by the 1. 84 3 2 MHz clock (PHI_ CTC clock, generated by U24, see A2l, 7-1).
The functions of the CTC timer outputs are shown in table 3-7.
Note that the CTCs are I/O addressable ports to the Z-80B CPU; their addresses are defined
In
table 3- 3.
Interfacing to the BIC
The Backplane Interface Circuit (BIC, see A 14, 7
-1)
provides the half -duplex data path to the I/O
channel (backplane). As used by the MUX card, the BIC is addressed as an I/O port by the Z- 8 OB
CPU (the same as the Z-80 SIO and CTC circuits). In other words,.to read or write from the BIC
registers, an IN or OUT instruction is executed to the I/O address of that register. The address space
of the BIC is described in table 3- 3.
Data can also be transferred between the BIC and memory directly under control of DMA chan-
nel B of the Memory Interface Circuit (MIC).
The BIC is not directly connected to the interrupt daisy chain structure of the MUX card.
Instead, the BIC's BINT- (interrupt output, see £14, 7-1) signal is connected to the MIC's IINT- (in-
terrupt
input, see C31,7
-1)
signal.
When the MIC is programmed for external interrupt (from
the RIC), the MIC will generate an interrupt for the BIC. The MIC also provides an interrupt
vector for the BIC when the Z- 80B CPU acknowledges.
Descriptions of the BIC signals are shown in table 3-8.
3-20
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